Germanium dual-fin field effect transistor
View Patent ↗In one example, a field effect transistor includes a pair of fins positioned in a spaced apart relation. Each of the fins includes germanium. Source and drain regions are formed on opposite ends of the pair of fins and include silicon. A gate is wrapped around the pair of fins, between the source and drain regions.
1. A field effect transistor comprising:
a substrate;
a pair of fins positioned in a spaced apart relation on the substrate, each of the fins in the pair of fins comprising germanium;
a high-k dielectric layer deposited over the substrate and the pair of fins, where the high-k dielectric layer directly contacts both the substrate and the pair of fins;
source and drain regions formed on opposite ends of the pair of fins, wherein the source and drain regions comprise silicon; and
a gate wrapped around the pair of fins, between the source and drain regions.
2. The field effect transistor of claim 1 , wherein the source and drain regions are formed of doped silicon.
3. The field effect transistor of claim 2 , further comprising:
an extension positioned beneath the source and drain regions, wherein the extension is formed of doped silicon.
4. The field effect transistor of claim 3 , wherein the extension is N + doped, and the doped silicon of the source and drain regions is N ++ doped.
5. The field effect transistor of claim 4 , wherein a doping concentration of the extension is between approximately 5e18 and 5e19 electrons per cubic centimeter, and a doping concentration of the source and drain regions is above approximately 1e20 electrons per cubic centimeter.
6. The field effect transistor of claim 1 , wherein the field effect transistor is an N-type field effect transistor.
7. The field effect transistor of claim 1 , wherein the germanium is epitaxially grown over silicon.
8. The field effect transistor of claim 3 , wherein the extension is P + doped, and the doped silicon of the source and drain regions is P ++ doped.
9. A field effect transistor comprising:
a substrate;
a pair of fins positioned in a spaced apart relation on the substrate, each of the fins in the pair of fins comprising a first semiconductor material;
a high-k dielectric layer deposited over the substrate and the pair of fins, where the high-k dielectric layer directly contacts both the substrate and the pair of fins;
source and drain regions formed on opposite ends of the pair of fins, wherein the source and drain regions comprise a second semiconductor material different from the first semiconductor material; and
a gate wrapped around the pair of fins, between the source and drain regions.
10. The field effect transistor of claim 9 , wherein the first semiconductor material is germanium.
11. The field effect transistor of claim 10 , wherein the germanium is epitaxially grown over the second semiconductor material.
12. The field effect transistor of claim 2 , wherein the extension is positioned directly between the substrate and the source and drain regions.
13. The field effect transistor of claim 1 , wherein the high-k dielectric layer is positioned between the source and drain regions without extending into the source and drain regions.
14. The field effect transistor of claim 9 , further comprising:
an extension positioned beneath the source and drain regions, wherein the extension is formed of a doped version of the second semiconductor material, wherein the extension is positioned directly between the substrate and the source and drain regions.
15. The field effect transistor of claim 14 , wherein the extension is N + doped, and the source and drain regions are N ++ doped.
16. The field effect transistor of claim 15 , wherein a doping concentration of the extension is between approximately 5e18 and 5e19 electrons per cubic centimeter, and a doping concentration of the source and drain regions is above approximately 1e20 electrons per cubic centimeter.
17. The field effect transistor of claim 9 , wherein the first semiconductor material is epitaxially grown over silicon.
18. The field effect transistor of claim 14 , wherein the extension is P + doped, and the source and drain regions are P ++ doped.
19. The field effect transistor of claim 9 , wherein the gate directly contacts the high-k dielectric layer.
20. The field effect transistor of claim 9 , wherein the high-k dielectric layer is positioned between the source and drain regions without extending into the source and drain regions.