SiGe FinFET with improved junction doping control
View Patent ↗A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a silicon substrate, a local oxide layer is formed on the silicon substrate, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and sidewall spacer layers; recessing the at least one SiGe fin in the source/drain region to the sidewall spacer layers and the silicon substrate layer; recessing the local oxide layer in the source/drain region to the sidewall spacer layer and the silicon substrate; growing a n-doped silicon layer on the silicon substrate; growing a p-doped silicon layer or p-doped SiGe layer on the n-doped silicon layer; and forming a silicide layer on the p-doped silicon layer or p-doped SiGe layer.
1. A method for fabricating a semiconductor device, the method comprising:
providing a FinFET having a source/drain region and at least one SiGe fin, wherein the at least one SiGe fin has sidewalls and is formed on a silicon substrate layer, a local oxide layer is formed on the silicon substrate layer, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and a plurality of sidewall spacer layers;
recessing the at least one SiGe fin in the source/drain region, wherein the at least one SiGe fin is recessed to the plurality of sidewall spacer layers and the silicon substrate layer;
recessing the local oxide layer in the source/drain region, wherein the local oxide layer is recessed to the plurality of sidewall spacer layers and the silicon substrate layer;
growing an n-doped silicon layer on the silicon substrate layer in the source/drain region;
growing either a p-doped silicon layer or a p-doped SiGe layer on the n-doped silicon layer in the source/drain region; and
forming a silicide layer on the p-doped silicon layer or the p-doped SiGe layer in the source/drain region.
2. The method according to claim 1 , wherein growing the n-doped silicon layer on the silicon substrate layer in the source/drain region further comprises:
etching the n-doped silicon layer from the at least one SiGe fin sidewalls; and etching under the plurality of sidewall spacer layers and the gate structure.
3. The method according to claim 2 , wherein etching the n-doped silicon layer comprises a HCI etch.
4. The method according to claim 1 , wherein recessing the at least one SiGe fin in the source/drain region exposes a portion of the silicon substrate layer in the source/drain region.
5. The method according to claim 1 , wherein recessing the at least one SiGe fin in the source/drain region further comprises growing an epitaxial layer to form an abrupt junction.
6. The method according to claim 1 , wherein recessing the local oxide layer in the source/drain region exposes the silicon substrate layer in the source/drain region.
7. The method according to claim 1 , wherein the n-doped silicon layer comprises a low to mid-e18/cm 3 n-type doping level.
8. The method according to claim 1 , wherein the n-doped silicon layer comprises a thickness between 10-30 nm.
9. The method according to claim 1 , wherein the p-doped silicon layer or the p-doped SiGe layer comprises a 2-4e 20 /cm 3 boron doping level.
10. The method according to claim 1 , wherein the p-doped silicon layer or p-doped SiGe layer comprises a thickness between 40-50 nm.
11. The method according to claim 1 , wherein the p-doped silicon layer or p-doped SiGe layer is grown using tetrasilane or trisilane.
12. A semiconductor device comprising:
a silicon substrate layer having a source/drain region;
a local oxide layer formed on the silicon substrate layer;
at least one SiGe fin formed on the silicon substrate layer, wherein the at least one SiGe fin includes an extension region, wherein the fin extension region is a SiGe fin region that extends vertically from the silicon substrate layer through the plurality of sidewall spacer layers;
a gate structure formed on the local oxide layer and the extension region of the at least one SiGe fin, wherein the gate structure is encapsulated by a plurality of sidewall spacer layers and a gate hard mask;
an n-doped silicon layer grown on the silicon substrate layer, wherein the n-doped silicon layer is grown in the source/drain region;
a p-doped silicon layer or p-doped SiGe layer grown on the n-doped silicon layer, wherein the p-doped silicon layer or p-doped SiGe layer is grown in the source/drain region; and
a silicide layer formed on the p-doped silicon layer or the p-doped SiGe layer, wherein the silicide layer is formed in the source/drain region.
13. The semiconductor device according to claim 11 , wherein the at least one SiGe fin forms an abrupt junction.
14. The semiconductor device according to claim 11 , wherein the n-doped silicon layer comprises a low to mid-e 18 /cm 3 n-type doping level.
15. The semiconductor device according to claim 11 , wherein the n-doped silicon layer comprises a thickness between 10-30 nm.
16. The semiconductor device according to claim 11 , wherein the p-doped silicon layer or the p-doped SiGe layer comprises a 2-4e 20 /cm 3 boron doping level.
17. The semiconductor device according to claim 11 , wherein the p-doped silicon layer or p-doped SiGe layer comprises a thickness between 40-50 nm.
18. The semiconductor device according to claim 11 , wherein the p-doped silicon layer or p-doped SiGe layer is grown using tetrasilane or trisilane.