CMOS fin integration on SOI substrate
View Patent ↗A method for complementary metal oxide semiconductor (CMOS) fin integration includes forming fin structures from a semiconductor layer of a silicon-on-insulator substrate and filling between the fin structures with a dielectric fill. The fin structures are masked in a first area while leaving top portions of the fin structures in a second area exposed. The fin structures are recessed in the second area to form trenches, and each trench has a fin portion remaining at a bottom thereof. A new fin is epitaxially grown in the trench from the fin portion. The new fin includes SiGe.
1. A method for complementary metal oxide semiconductor (CMOS) fin integration, comprising:
forming fin structures from a semiconductor layer of a silicon-on-insulator substrate;
filling between the fin structures with a dielectric fill;
masking the fin structures in a first area while leaving top portions of the fin structures in a second area exposed;
recessing the fin structures in the second area to form trenches, each trench having a fin portion remaining at a bottom thereof; and
epitaxially growing a new fin in the trench from the fin portion, the new fin including SiGe.
2. The method as recited in claim 1 , wherein the first area includes a region for N-type field effect transistors (NFETs) and the second area includes a region for P-type field effect transistors (PFETs).
3. The method as recited in claim 1 , wherein epitaxially growing the new fin includes epitaxially growing the new fin with a Ge concentration of over 50 atomic %.
4. The method as recited in claim 1 , wherein epitaxially growing the new fin includes epitaxially growing the new fin with a Ge concentration of over 90 atomic %.
5. The method as recited in claim 1 , wherein epitaxially growing the new fin includes epitaxially growing the new fin to a height of at least 30 nm.
6. The method as recited in claim 1 , wherein recessing the fin structures includes recessing the fins to between about 5 nm to about 10 nm in height.
7. The method as recited in claim 1 , wherein the trenches include a width of between about 20 nm to about 150 nm.
8. The method as recited in claim 1 , further comprising thermally mixing Ge from the new fin into the fin portion.
9. The method as recited in claim 1 , wherein the step of epitaxially growing is independent of Ge concentration.
10. A method for complementary metal oxide semiconductor (CMOS) fin integration, comprising:
forming fin structures from a silicon layer of a silicon-on-insulator substrate;
forming a dielectric fill between the fin structures;
exposing top portions of the fin structures by removing a portion of the dielectric fill;
designating an N-type field effect transistor (NFET) region and P-type field effect transistor (PFET) region on the substrate;
masking the NFET region;
recessing the fin structures in the PFET region to form trenches within the dielectric fill, each trench having a silicon portion remaining at a bottom thereof;
epitaxially growing a SiGe fin in the trench from the silicon portion; and
thermally mixing Ge from the SiGe fin into the silicon portion.
11. The method as recited in claim 10 , wherein epitaxially growing the SiGe fin includes epitaxially growing the SiGe fin with a Ge concentration of over 50 atomic %.
12. The method as recited in claim 10 , wherein epitaxially growing the SiGe fin includes epitaxially growing the SiGe fin with a Ge concentration of over 90 atomic %.
13. The method as recited in claim 10 , wherein epitaxially growing the SiGe fin includes epitaxially growing the SiGe fin to a height of at least 30 nm.
14. The method as recited in claim 10 , wherein recessing the fin structures includes recessing the fins to between about 5 nm to about 10 nm in height.
15. The method as recited in claim 10 , wherein the trenches include a width of between about 20 nm to about 150 nm.
16. The method as recited in claim 10 , wherein the step of epitaxially growing is independent of Ge concentration.
17. A method for complementary metal oxide semiconductor (CMOS) fin integration, comprising:
forming fin structures from a silicon layer of a silicon-on-insulator substrate;
forming a dielectric fill between the fin structures;
exposing top portions of the fin structures by removing a portion of the dielectric fill;
designating an N-type field effect transistor (NFET) region and P-type field effect transistor (PFET) region on the substrate;
masking the NFET region;
recessing the fin structures in the PFET region to form trenches within the dielectric fill, each trench having a silicon portion remaining at a bottom thereof;
epitaxially growing a SiGe fin in the trench from the silicon portion, for which growth is independent of Ge concentration such that a Ge concentration of over 90 atomic % is provided; and
thermally mixing Ge from the SiGe fin into the silicon portion.
18. The method as recited in claim 17 , wherein epitaxially growing the SiGe fin includes epitaxially growing the SiGe fin to a height of at least 30 nm.
19. The method as recited in claim 17 , wherein recessing the fin structures includes recessing the fins to between about 5 nm to about 10 nm in height.
20. The method as recited in claim 17 , wherein the trenches include a width of between about 20 to about 150 nm.