IP Library Granted Patent US 9,997,630
Granted Patent B2
US 9,997,630 · App. 15/338,535 · Granted Jun 12, 2018

Charge carrier transport facilitated by strain

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Quick Facts
Patent No.
US 9,997,630
App. No.
15/338,535
Granted
Jun 12, 2018
Kind
B2
Abstract

A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.

Claims (18)

1. A semiconductor structure comprising:

a first semiconductor layer with a first lattice structure;

a second semiconductor layer that is lattice-matched and in contact with the first semiconductor layer; and

at least two source/drain regions with a second lattice structure, wherein the source/drain regions are in contact the second semiconductor layer and the first semiconductor layer, wherein at least a portion of the second semiconductor layer is between the source/drain regions, wherein the at least portion has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.

2. The semiconductor structure of claim 1 , wherein the first semiconductor layer is further comprised of a semi-insulating semiconductor material.

3. The semiconductor structure of claim 1 , wherein one or both of: the second semiconductor layer and the source/drain regions are further comprised of compound semiconductors.

4. The semiconductor structure of claim 1 , wherein one or both of: the second semiconductor layer and the source/drain regions are further comprised of ternary semiconductors.

5. The semiconductor structure of claim 1 , wherein one or both of: the second semiconductor layer and the source/drain regions are further comprised of III-V semiconductors.

6. The semiconductor structure of claim 1 , wherein one or both of: the second semiconductor layer and the source/drain regions include indium.

7. The semiconductor structure of claim 1 , wherein one or both of: the second semiconductor layer and the source/drain regions are further comprised of alloys of indium arsenide and gallium arsenide.

8. The semiconductor structure of claim 1 , wherein the second semiconductor layer is further comprised of In 0.53 Ga 0.47 As and the source/drain regions are further comprised of In y Ga (1−y) As, and wherein y has a range between approximately 0.53 and 1.

9. The semiconductor structure of claim 1 , wherein the second semiconductor layer is further comprised of In 0.53 Ga 0.47 As and the source/drain regions are further comprised of In y Ga (1−y) As, and wherein y has a range between 0 and approximately 0.53.

10. A semiconductor structure comprising:

a semi-insulating semiconductor layer;

a semiconductor layer composed of In 0.53 Ga 0.47 As, wherein the semiconductor layer is epitaxial with the semi-insulating semiconductor layer, wherein the semiconductor layer is lattice-matched with the semi-insulating semiconductor layer; and

at least two source/drain regions composed of In y Ga (1−y) As, wherein y has a range between 0 and 1, wherein the source/drain regions penetrate the semiconductor layer and contact the semi-insulating semiconductor layer, wherein the source/drain regions are lattice-mismatched with the semi-insulating semiconductor layer and the semiconductor layer, wherein a portion of the semiconductor layer is between source/drain regions, wherein the portion has a degree of uniaxial strain that is based, at least in part, on the lattice-mismatch between the source/drain regions and both the semi-insulating semiconductor layer and the semiconductor layer.

11. The semiconductor structure of claim 10 , wherein y has a range between approximately 0.53 and 1.

12. The semiconductor structure of claim 10 , wherein y has a range between 0 and approximately 0.53.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052620/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2016
From: BASU, ANIRBAN; COHEN, GUY M.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 040171/0806 →