CMOS compatible fuse or resistor using self-aligned contacts

1. A semiconductor device, comprising:

dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween;

a trench silicide structure formed in the gap on the dielectric layer and extending longitudinally beyond the gap on end portions, the trench silicide structure forming a resistive element; and

self-aligned contacts formed through an interlevel dielectric layer and landing on the trench silicide structure beyond the gap on the end portions, wherein the self-aligned contacts wrap-around a sidewall portion of the trench silicide structure.

2. The device as recited in claim 1 , wherein the trench silicide structures are concurrently formed in active regions for active field effect transistors as a source/drain contact.

3. The device as recited in claim 2 , wherein the self-aligned contacts are concurrently formed in the active regions as a contact to the source/drain contact.

4. The device as recited in claim 1 , wherein the dummy gate structures include a gate conductor, a gate dielectric and sidewall spacers as concurrently formed in active regions for active field effect transistors.

5. The device as recited in claim 1 , wherein the resistive element includes a fuse.

6. The device as recited in claim 1 , wherein the resistive element includes a vertical plane disposed transversely with the substrate between the dummy gate structures.

7. A semiconductor device, comprising:

first gate structures and second gate structures formed concurrently with the first gate structures formed in an active area and the second gate structures formed on a dielectric layer over a substrate outside the active area;

a trench silicide structure formed between the first gate structures in the active area and between the second gate structures outside the active area, the trench silicide structure in the active area forming a contact to a source/drain region and the trench silicide structure outside the active area forming a resistive element on the dielectric layer; and

self-aligned contacts formed through an interlevel dielectric layer and landing on the trench silicide structure in the active areas to extend the source/drain contact and the self-aligned contacts outside the active area including connections to end portions of the resistive element.

8. The device as recited in claim 7 , wherein the end portions of trench silicide structure outside the active area extend longitudinally beyond a gap formed between the second gate structures.

9. The device as recited in claim 7 , wherein the first and second gate structures include a gate conductor, a gate dielectric and sidewall spacers.

10. The device as recited in claim 7 , wherein the resistive element includes a fuse.

11. The device as recited in claim 7 , wherein the self-aligned contacts wrap-around a sidewall portion of the trench silicide structure.

12. The device as recited in claim 7 , wherein the resistive element includes a vertical plane disposed transversely with the substrate between adjacent second gate structures.

13. A method for fabricating a resistive element on a semiconductor device, comprising:

forming dummy gate structures on a dielectric layer over a substrate with a gap therebetween;

forming a trench silicide structure in the gap on the dielectric layer and extending longitudinally beyond the gap on end portions, the trench silicide structure forming a resistive element; and

forming self-aligned contacts through an interlevel dielectric layer and landing on the trench silicide structure beyond the gap on the end portions; and

wrapping the self-aligned contacts around a sidewall portion of the trench silicide structure.

14. The method as recited in claim 13 , wherein the dummy gate structures, the trench silicide structure and the self-aligned contacts are concurrently formed with corresponding elements in active regions for active field effect transistors.

15. The method as recited in claim 13 , wherein the resistive element includes one of a fuse or a resistor.

16. The method as recited in claim 13 , wherein the resistive element includes a vertical plane disposed transversely with the substrate between the dummy gate structures.