Semiconductor device having self-aligned gate contacts
A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact.
1. A semiconductor device comprising:
a first dielectric layer formed over a semiconductor device having a plurality of gate structures formed on a plurality of active regions and a plurality of diffusion regions formed alongside the plurality of active regions, wherein the plurality of gate structures have a top, a bottom, and two sides, and are encapsulated by an insulating layer on the top and two sides;
a plurality of first trenches formed at a plurality of first locations through the first dielectric layer to a first portion of the plurality of diffusion regions, wherein silicide is formed on the first portion of the plurality of diffusion regions and the plurality of first trenches are filled with an insulating material, wherein the insulating material is different from a material of the first dielectric layer;
at least one first gate contact formed through the first dielectric layer and the insulating layer on the top at least one of the plurality of gate structures, wherein the at least one first gate contact is filled with a first contact fill and formed between the plurality of first trenches;
a second dielectric layer deposited on the first dielectric layer, the plurality of first filled trenches, and the at least one filled gate contact;
a plurality of second trenches formed at a plurality of second locations through the first and second dielectric layers to a second portion of the plurality of diffusion regions, wherein silicide is formed on the second portion of the plurality of diffusion regions and the plurality of second trenches are filled with a conductive material, wherein the plurality of second trenches filled with the conductive material and the plurality of the first trenches filled with the insulating material are at non-overlapping locations; and
at least one second gate contact through the second dielectric layer, wherein the at least one second gate contact is filled with a second contact fill and is in contact with the at least one first gate contact.
2. The device according to claim 1 , wherein the first and second dielectric layers comprise a first middle of the line dielectric.
3. The device according to claim 1 , wherein the insulating material is a second middle of the line dielectric.
4. The device according to claim 3 , wherein the second middle of the line dielectric is silicon nitride.
5. The device according to claim 1 , wherein the conductive material, the first contact fill, and the second contact fill is a metal.
6. The device according to claim 5 , wherein the metal is selected from a group consisting of: titanium, titanium nitride, tungsten, aluminum, copper, platinum, tantalum, tantalum nitride, and combinations thereof.
7. The device according to claim 1 , wherein the plurality of first trenches extend a distance through the first dielectric layer and the at least one first gate contact extends a distance through the first dielectric layer.
8. The device according to claim 7 , wherein the distance of the at least one first gate contact through the first dielectric layer is less than the distance of the plurality of first trenches through the first dielectric layer.
9. The device according to claim 1 , wherein the plurality of gate structures have a pitch of 50-100 nanometers.
10. The device according to claim 1 , wherein the first dielectric layer includes SiO 2 .
11. The device according to claim 1 , wherein the first dielectric layer includes SiCOH.
12. The device according to claim 1 , wherein the plurality of first trenches formed at the plurality of first locations correspond to a midpoint of the plurality of gate structures.
13. The device according to claim 1 , wherein the insulating material includes silicon nitride.
14. The device according to claim 1 , wherein the at least one first gate contact is shorter than the plurality of first trenches.
15. The device according to claim 1 , wherein the plurality of second trenches are at an endpoint of the plurality of gate structures.
16. The device according to claim 1 , wherein the plurality of second trenches are at a midpoint of the plurality of gate structures; and
wherein the plurality of first trenches are at an endpoint of the plurality of gate structures.
17. The device according to claim 1 , wherein the at least one second gate contact does not touch the plurality of second trenches.
18. The device according to claim 1 , wherein the at least one second gate contact are separated from the plurality of second trenches.
19. The device according to claim 18 , wherein a part of the plurality of first trenches separates the at least on second gate from the plurality of second trenches.
20. A semiconductor device comprising:
a first dielectric layer formed over a semiconductor device, the semiconductor device having a plurality of gate structures formed on a plurality of active regions and a plurality of diffusion regions formed alongside the plurality of active regions, wherein the plurality of gate structures are encapsulated on a top and two sides by an insulating layer;
first filled trenches formed at first locations through the first dielectric layer and at a first portion of the plurality of diffusion regions, wherein silicide is formed on the first portion of the plurality of diffusion regions and the first filled trenches are filled with an insulating material, wherein the insulating material is different from a material of the first dielectric layer;
at least one first gate contact formed through the first dielectric layer and the insulating layer on the top at least one of the plurality of gate structures, wherein the at least one first gate contact is formed between the first filled trenches;
a second dielectric layer deposited on the first dielectric layer, the first filled trenches, and the at least one first gate contact;
second filled trenches formed at second locations through the first and second dielectric layers and at a second portion of the plurality of diffusion regions, wherein silicide is formed on the second portion of the plurality of diffusion regions and the second trenches are filled with a conductive material, wherein the second filled trenches filled with the conductive material and the first filled trenches filled with the insulating material are at non-overlapping locations; and
at least one second gate contact through the second dielectric layer, the at least one second gate contact in contact with the at least one first gate contact.