Multi-orientation SOI substrates for co-integration of different conductivity type semiconductor devices
View Patent ↗A method of forming a semiconductor device that includes providing a base semiconductor substrate having a first orientation crystal plane, and forming an epitaxial oxide layer on the base semiconductor substrate. The epitaxial oxide layer has the first orientation crystal plane. A first semiconductor layer having a second orientation crystal plane is then bonded to the epitaxial oxide layer. A portion of the first semiconductor layer is removed to expose a second surface of the epitaxial oxide layer. A remaining portion of the first semiconductor layer is present on the first surface of the epitaxial oxide layer; and epitaxially forming a second semiconductor layer on the second surface of the epitaxial oxide layer, wherein the second semiconductor layer has a first orientation crystal plane.
1. A semiconductor device comprising:
a base substrate comprised of a semiconductor material having a first orientation crystal plane;
an epitaxial oxide layer present directly on the base substrate and having the first orientation crystal plane, wherein an entirety of the epitaxial oxide layer has the first orientation crystal plane;
a first semiconductor layer having a second orientation crystal plane that is different from the first orientation crystal plane present directly on a first portion of the epitaxial oxide layer having the first orientation crystal plane, the first semiconductor layer providing at least the channel region of first conductivity semiconductor device; and
a second semiconductor layer present directly on a second portion of the epitaxial oxide layer that has the first orientation crystal plane, the second semiconductor layer provides at least the channel region of second conductivity semiconductor device.
2. The semiconductor device of claim 1 , wherein the first orientation crystal plane is (100), the second orientation crystal plane is (110), the first conductivity semiconductor device is a p-type semiconductor device, and the second conductivity semiconductor device is an n-type semiconductor device.
3. The semiconductor device of claim 1 , wherein the first orientation crystal plane is (110), the second orientation crystal plane is (100), the first conductivity semiconductor device is an n-type semiconductor device, and the second conductivity semiconductor device is a p-type semiconductor device.
4. The semiconductor device of claim 1 , wherein the base substrate comprises a silicon containing material selected from the group consisting of Si, SiGe, Ge, Si:C (silicon doped with carbon), SiGe:C, and combinations thereof.
5. The semiconductor device of claim 1 , wherein the epitaxial oxide layer is an oxide including a rare earth metal selected from the group consisting of Lanthanum (La), Cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Luthium (Lu), and a combination thereof.
6. The semiconductor device of claim 1 , wherein the epitaxial oxide layer is selected from the group consisting of (La x Y 1-x ) 2 O 3 , CeO 2 , and combinations thereof.
7. The semiconductor device of claim 1 , wherein the first semiconductor layer is an epitaxial material.
8. The semiconductor device of claim 5 , wherein the first semiconductor layer is lattice matched to the epitaxial oxide layer.
9. The semiconductor device of claim 1 , wherein the first semiconductor layer comprises a first silicon containing material selected from the group consisting of Si, SiGe, Ge, Si:C (silicon doped with carbon), SiGe:C, and combinations thereof; and the second semiconductor layer comprises a second silicon containing material selected from the group consisting of Si, SiGe, Ge, Si:C (silicon doped with carbon), SiGe:C, and combinations thereof.
10. The semiconductor device of claim 1 , wherein an interface between the second semiconductor layer and the epitaxial oxide layer is a bonded interface.
11. The semiconductor device of claim 8 , wherein there is a lattice mismatch between the second semiconductor layer and the epitaxial oxide layer.
12. The semiconductor device of claim 2 , wherein the first semiconductor layer provides a first fin structure for a p-type FinFET, wherein the first fin structure is orientated so that hole charge carriers travel along a <110> orientation direction, and the second semiconductor layer provides a second fin structure for an n-type FinFET, wherein the second fin structure is orientated so that electron charge carrier travel along a <100> orientation direction.
13. The semiconductor device of claim 1 , wherein the first semiconductor layer has a thickness of less than 10 nm to provide the channel of an extremely thin semiconductor on insulator (ETSOI) p-type semiconductor device that is planar, and the second semiconductor layer has a thickness of less than 10 nm to provide the channel of an extremely thin semiconductor on insulator (ETSOI) n-type semiconductor device that is planar.
14. A semiconductor device comprising:
a base substrate comprised of a semiconductor material having a (100) orientation crystal plane;
an epitaxial oxide layer present directly on the base substrate, the epitaxial oxide layer having a (100) orientation crystal plane in its entirety;
a first semiconductor layer having said (110) orientation crystal plane present directly on a first portion of the epitaxial oxide layer having said (100) orientation crystal plane, the first semiconductor layer providing at least the channel region of a p-type conductivity semiconductor device; and
a second semiconductor layer having a (100) orientation crystal plane present directly on a second portion of the epitaxial oxide layer having said (100) orientation crystal plane, the second semiconductor layer provides at least the channel region of an n-type conductivity semiconductor device.
15. A method of forming a semiconductor device comprising:
providing a base semiconductor substrate having a first orientation crystal plane;
forming an epitaxial oxide layer on base semiconductor substrate, wherein an entirety of the epitaxial oxide has the first orientation crystal plane;
bonding a first semiconductor layer having a second orientation crystal plane to the epitaxial oxide layer having the first orientation crystal plane;
removing a portion of the first semiconductor layer to expose a second surface of the epitaxial oxide layer, wherein a remaining portion of the first semiconductor layer is present on the first surface of the epitaxial oxide layer; and
epitaxially forming a second semiconductor layer on the second surface of the epitaxial oxide layer, wherein the second semiconductor layer has a first orientation crystal plane, wherein the remaining portion of the first semiconductor layer provides the channel region of a first conductivity semiconductor device and the second semiconductor layer provides the channel region of a second conductivity semiconductor device.
16. The method of claim 15 , wherein the first orientation crystal plane is (110) and the second orientation crystal plane is (100), wherein the first conductivity semiconductor device is a p-type semiconductor device, and the second conductivity semiconductor device is an n-type semiconductor device.
17. The method of claim 15 , wherein the epitaxial oxide layer is an oxide including a rare earth metal selected from the group consisting of Lanthanum (La), Cerium (Ce), Praseodymium (Pr), Neodymium (Nd), Promethium (Pm), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Luthium (Lu), and a combination thereof.
18. The method of claim 15 , wherein the first semiconductor layer comprises a first silicon containing material selected from the group consisting of Si, SiGe, Ge, Si:C (silicon doped with carbon), SiGe:C, and combinations thereof and the second semiconductor layer comprises a second silicon containing material selected from the group consisting of Si, SiGe, Ge, Si:C (silicon doped with carbon), SiGe:C, and combinations thereof.
19. The method of claim 15 , further comprising:
etching the first and second semiconductor layers to provide a first set of fin structures composed of material from the first semiconductor layer, and a second set of fin structures composed of material from the second semiconductor layer;
forming a gate structure on the channel region portions of the first and second set of fin structures; and
forming source and drain regions in the portions of the first and second fin structures that are present on opposing sides of the gate structure.
20. The method of claim 15 further comprising forming at least one gate structure on the first and second semiconductor layers, and forming source and drain regions in the first and second semiconductor layers on opposing sides of the at least one gate structure to provide at least one planar first conductivity semiconductor device on the first semiconductor layer, and at least one planar second conductivity semiconductor device on the second semiconductor layer.