High-K spacer for extension-free CMOS devices with high mobility channel materials
View Patent ↗A field effect transistor device includes a gate structure formed over a channel region in a semiconductor material. An inner spacer is formed on sidewalls of the gate structure and over an extension region of the semiconductor material. The inner spacer includes charge or dipoles. A source/drain region is formed adjacent to the gate structure. An inversion layer is formed in the extension region induced by the inner spacer to form a conductive link between the channel region and the source/drain region.
1. A field effect transistor device, comprising:
a gate structure formed over a channel region in a semiconductor material;
an inner spacer formed directly on sidewalls of the gate structure and over an extension region of the semiconductor material, where the inner spacer is a dielectric material with a dielectric constant greater than about 7, and the inner spacer including charge or dipoles;
a source/drain region formed adjacent to the gate structure; and
an inversion layer formed in the extension region induced by the inner spacer to form a conductive link between the channel region and the source/drain region.
2. The device as recited in claim 1 , further comprising an outer spacer formed on the inner spacer.
3. The device as recited in claim 1 , wherein the inner spacer includes one of an oxide of the lanthanide series, an oxide of an alkaline earth metals or HfON for an n-type field effect transistor.
4. The device as recited in claim 1 , wherein the inner spacer includes one of Al 2 O 3 , TiO 2 , or HfO 2 for a p-type field effect transistor.
5. The device as recited in claim 1 , wherein the source/drain region includes an in-situ doped region to avoid dopant processing in the extension region and the channel region.
6. The device as recited in claim 1 , wherein the transistor includes a complementary metal oxide semiconductor (CMOS) device and the semiconductor material includes a first semiconductor layer for forming n-type field effect transistors (NFETs) and a second semiconductor layer for forming p-type field effect transistors (PFETs).
7. The device as recited in claim 6 , wherein the first semiconductor layer includes a III-V material and the second semiconductor layer includes SiGe.
8. The device as recited in claim 1 , wherein the inner spacer includes positive charge or dipoles and the inversion layer includes an electron inversion layer for n-type field effect transistors.
9. The device as recited in claim 1 , wherein the inner spacer includes negative charge or dipoles and the inversion layer includes a hole inversion layer for p-type field effect transistors.
10. A field effect transistor device, comprising:
a complementary metal oxide semiconductor (CMOS) device having a first semiconductor material for forming n-type field effect transistors (NFETs) and a second semiconductor material for forming p-type field effect transistors (PFETs), the first and second semiconductor materials being formed from different materials on a same substrate;
gate structures formed over channel regions in the first and second semiconductor materials;
first inner spacers formed directly on sidewalls of the gate structures of NFETS and over extension regions of the first semiconductor material, the first inner spacers including positive charge or dipoles;
second inner spacers formed directly on sidewalk of the gate structures of PFETS and over extension regions of the second semiconductor material, the second inner spacers including negative charge or dipoles, wherein the first and second inner spacers include a dielectric material with a dielectric constant greater than about 7;
source/drain regions formed adjacent to the gate structures; and
inversion layers formed in the extension regions between the channel regions and the source/drain regions, the inversion layers being induced by the first and second inner spacers to form a conductive link between the channel regions and the source/drain regions.
11. The device as recited in claim 10 , further comprising an outer spacer formed on the first and second inner spacers.
12. The device as recited in claim 10 , wherein the first inner spacers include one of an oxide of the lanthanide series, an oxide of an alkaline earth metals or HfON for an n-type field effect transistor.
13. The device as recited in claim 10 , wherein the second inner spacers include one of Al 2 O 3 , TiO 2 , or HfO 2 for a p-type field effect transistor.
14. The device as recited in claim 10 , wherein the source/drain regions include situ doped regions to avoid dopant processing in the extension region and the channel region.
15. The transistor as recited in claim 10 , wherein the first semiconductor material includes a III-V material and the second semiconductor material includes SiGe.