IP Library Granted Patent US 9,312,132
Granted Patent B2
US 9,312,132 · App. 14/701,213 · Granted Apr 12, 2016

Method of forming high-density arrays of nanostructures

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Quick Facts
Patent No.
US 9,312,132
App. No.
14/701,213
Granted
Apr 12, 2016
Kind
B2
Abstract

A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.

Claims (42)

1. A method for forming nanostructures, comprising:

bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate;

stressing the crystalline semiconductor layer in a first direction to initiate first cracks in the semiconductor layer;

propagating the first cracks through the semiconductor layer and through the two-dimensional material; and

releasing stress on the semiconductor layer to provide parallel structures including the two-dimensional material on the semiconductor layer.

2. The method as recited in claim 1 , wherein the semiconductor layer comprises a crystalline semiconductor material.

3. The method of claim 1 further comprising forming the crystalline semiconductor layer on the two-dimensional material, wherein the two-dimensional material is directly present on a semiconductor substrate.

4. The method of claim 3 further comprising removing the semiconductor substrate after said bonding the flexible substrate to the semiconductor layer.

5. The method of claim 3 , wherein the two dimensional material is carbon containing material.

6. The method of claim 3 , wherein the semiconductor substrate is a monocrystalline substrate.

7. The method as recited in claim 1 , wherein propagating cracks includes computing a strain corresponding with an intercrack distance and applying the strain to provide a dimension for the parallel structures that is equal to the intercrack distance.

8. The method as recited in claim 1 , wherein the two-dimensional material includes graphene and the crystalline semiconductor layer includes SiC.

9. The method as recited in claim 1 , further comprising:

bending the crystalline semiconductor layer in accordance with a second direction to initiate second cracks transversely to the first cracks;

propagating the second cracks through the crystalline semiconductor layer and through the two-dimensional material; and

releasing stress on the crystalline semiconductor layer to provide dot structures including the two-dimensional material on the crystalline semiconductor layer.

10. The method as recited in claim 1 , further comprising: forming an electronic or photonic device with the parallel structures.

11. The method as recited in claim 1 , further comprising:

providing a monocrystalline semiconductor substrate;

forming at least two monolayers of a two-dimensional material on the substrate;

epitaxially growing a crystalline semiconductor layer over the two-dimensional material; and

separating the substrate from the crystalline semiconductor layer, which is bonded to the flexible substrate by splitting the two dimensional material.

12. The method as recited in claim 1 , wherein stressing includes bending the the crystalline semiconductor layer using a two point bend or over a radiused surface.

13. The method as recited in claim 1 , wherein propagating includes applying one or more of a temperature change, vibration, and increased stress.

14. A method for forming nanostructures, comprising:

providing a monocrystalline semiconductor substrate;

forming at least two monolayers of a two-dimensional material on the substrate;

epitaxially growing a crystalline semiconductor layer over the two-dimensional material;

bonding a flexible substrate to the crystalline semiconductor layer;

separating the substrate from the crystalline semiconductor layer, which is bonded to the flexible substrate by splitting the two dimensional material;

stressing the crystalline semiconductor layer in a first direction to initiate first cracks in the crystalline semiconductor layer;

propagating the first cracks through the crystalline semiconductor layer and through the two-dimensional material; and

releasing stress on the crystalline semiconductor layer to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.

15. The method as recited in claim 14 , wherein propagating cracks includes computing a strain corresponding with an intercrack distance and applying the strain to provide a dimension for the parallel structures that is equal to the intercrack distance.

16. The method as recited in claim 14 , wherein the two-dimensional material includes graphene and the crystalline semiconductor layer includes SiC.

17. The method as recited in claim 14 , further comprising: forming an electronic or photonic device with the parallel structures.

18. The method as recited in claim 14 , further comprising:

bending the crystalline semiconductor layer in accordance with a second direction to initiate second cracks transversely to the first cracks;

propagating the second cracks through the crystalline semiconductor layer and through the two-dimensional material; and

releasing stress on the crystalline semiconductor layer to provide dot structures including the two-dimensional material on the crystalline semiconductor layer.

19. The method as recited in claim 14 , wherein stressing includes bending the the crystalline semiconductor layer using a two point bend or over a radiused surface.

20. The method as recited in claim 14 , wherein propagating includes applying one or more of a temperature change, vibration, and increased stress.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052620/0961 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2015
From: DIMITRAKOPOULOS, CHRISTOS D.; KIM, JEEHWAN; PARK, HONGSIK; SHIN, BYUNGHA
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 035541/0001 →