IP Library Granted Patent US 8,772,941
Granted Patent B2
US 8,772,941 · App. 12/206,314 · Granted Jul 8, 2014

Circuit structure with low dielectric constant regions

Inventors: Lawrence A. Clevenger (LaGrangeville, NY); Matthew E. Colburn (Hopewell Junction, NY); Louis C. Hsu (Fishkill, NY); Wai-Kin Li (Beacon, NY)
Assignee: International Business Machines Corporation
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Quick Facts
Patent No.
US 8,772,941
App. No.
12/206,314
Granted
Jul 8, 2014
Kind
B2
Abstract

A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

Claims (9)

1. An electrical circuit structure, comprising:

at least two generally parallel conductor structures;

a solid dielectric material generally interposed between said at least two generally parallel conductor structures;

a pinching dielectric material, separate and distinct from said solid dielectric material, wherein said pinching dielectric material is homogeneous and is in contact with said solid dielectric material;

a plurality of relatively low dielectric constant (low-k) volumes located within said solid dielectric material between said at least two generally parallel conductor structures and surrounded and sealed by a composition of said pinching dielectric material and a barrier;

wherein said relatively low-k volumes are structurally configured to reduce parasitic capacitance between said at least two generally parallel conductor structures as compared to an otherwise comparable circuit not including said relatively low-k volumes

wherein said relatively low dielectric constant (low-k) volumes contain substantially gaseous material;

wherein said solid dielectric material generally defines a dielectric material stack; and said at least two generally parallel conductor structures comprise metallized dual-damascened via line structures in a same plane as said dielectric material stack.

2. The structure of claim 1 wherein said two parallel conductor structures comprise a transmission line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052620/0961 →
Continuity (2)
Division 11623478 · Jan 16, 2007
Related Publication 20090008791A1 · Jan 8, 2009