Output filter for delta sigma modulator and digital signal processor provided with the same
The invention intends to reduce noises by resistors in an output filter for a delta sigma modulator. The output filter uses an FIR filter with constant current sources as the current source, extracts output data of the delta sigma modulator from each taps of a shift register, controls MOS transistors by the extracted delayed signals, attains currents weighted according to the FIR filter coefficients corresponding to the number of the taps from the constant current sources, adds the currents attained, and performs the current-to-voltage conversion of the currents thus attained by feedback resistors of a full differential operational amplifier.
1. An output filter for a delta sigma modulator, comprising:
a first and a second constant current source having first and second outputs, respectively;
a FIR filter having a plurality n of delay element arranged in cascade, where n is a whole number greater than two, each element being operative to output data of the delta sigma modulator by controlling currents via n switches from the first and second constant current sources on the basis of each of the output data to thereby generate a plurality of weighted currents that are weighted according to a filter characteristic, the weighted currents being added separately for inverted and non-inverted signals and outputted separately at an output side of the FIR filter; and
a current-to-voltage conversion unit, said unit having an input side coupled to the output side of the FIR filter and comprising a full differential operational amplifier and feed back resistors, said amplifier having a pair of inputs, each input coupled to a respective one of each separate output of said FIR filter and having an output side.
2. An output filter for a delta sigma modulator as claimed in claim 1 , farther comprising a single differential conversion operational amplifier on the output side of the fall differential operational amplifier.
3. A digital signal processor comprising an output filter for a delta sigma modulator, as claimed in claim 1 or claim 2 .
4. An output filter for a delta sigma modulator as claimed in claim 1 , wherein each said n delay element comprises a flip-flop and each said n switches comprises a respective pair of MOS transistors.
5. An output filter for a delta sigma modulator as claimed in claim 4 , wherein said flip flop generates two outputs and each said output is coupled to a gate of a respective one of the MOS transistors.
6. An output filter for a delta sigma modulator as claimed in claim 1 , wherein each said constant current source comprises a common source for generating said plurality of weighted currents.