IP Library Granted Patent US 7,078,339
Granted Patent B2
US 7,078,339 · App. 10/731,482 · Granted Jul 18, 2006

Method of forming metal line layer in semiconductor device

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Quick Facts
Patent No.
US 7,078,339
App. No.
10/731,482
Granted
Jul 18, 2006
Kind
B2
Abstract

The present invention is provided to form a metal line layer in a semiconductor device, wherein at least one conductive layer of a plurality of conductive layers is etched, a side wall oxide film is formed on side walls of some conductive layers of the etched conductive layers, and then the other conductive layers are etched. According to the present invention, since it is possible to prevent attacks against the side walls, which may occur due to sputtering and bending of plasma ions, it is possible to enhance yield and reliability of a semiconductor device.

Claims (24)

1. A method of forming a metal line layer in a semiconductor device, comprising:

depositing a diffusion barrier layer, a metal layer and an anti reflection layer on a semiconductor substrate;

depositing an insulating film on the anti reflection layer;

depositing and patterning a photosensitive material on the insulating film;

etching portions of the insulating film, the anti reflection layer and the metal layer using activated plasma and the photosensitive material as a mask, whereby a portions of side walls of the metal layer are over-etched by plasma ions;

removing the photosensitive material;

forming a side wall oxide film on the over-etched side walls of the metal layer by reacting the metal layer with ozone; and

etching portions of the diffusion barrier layer using the insulating film and the side wall oxide film as an etch mask.

2. A method of forming a metal line layer in a semiconductor device according to claim 1 , wherein the metal layer is made of aluminum (Al).

3. A method of forming a metal line layer in a semiconductor device according to claim 1 , wherein the diffusion barrier layer is made of Ti/TiN layer, and the anti reflection layer is made of Ti/TiN layer, and the side wall oxide film is an Al 2 O 3 film.

4. A method of forming a metal line in a semiconductor memory device according to claim 1 , wherein the the anti reflection layer, the metal layer and the diffusion barrier layer are dry-etched using activated plasma comprising Cl 2 /BCl 3 /N 2 gas.

5. A method of forming a metal line in a semiconductor device according to claim 1 , wherein the insulating film is a nitride film.

6. A method of forming a metal line in a semiconductor device according to claim 1 , wherein the insulating film is etched by means of a dry etching process using activated plasma comprising a combination of CHF 3 /CF 4 /Ar or C x F y (where x, y are natural numbers)/O 2 /Ar gas.

7. A method of forming a metal line layer in a semiconductor device, comprising:

depositing a first, second and third conductive layers on a semiconductor substrate;

depositing an insulating film on the third conductive layer;

dry etching portions of the insulating film, the third and the second conductive layers using activated plasma, whereby a portions of side walls of the second conductive layer are over-etched by plasma ions;

forming a side wall oxide film on the side walls of the over-etched second conductive layer by reacting the second conductive layer with ozone; and

etching portions of the first conductive layer using the insulating film and the side wall oxide film as an etch mask.

8. A method of forming a metal line layer in a semiconductor device according to claim 7 , wherein the first conductive layer is made of Ti/TiN layer, the second conductive layer is made of aluminum (Al), and the third conductive layer is made of Ti/TiN layer.

9. A method of forming a metal line layer in a semiconductor device according to claim 9 , wherein the side wall oxide film is an Al 2 O 3 film.

10. A method of forming a metal line in a semiconductor device according to claim 7 , wherein the insulating film is a nitride film.

11. A method of forming a metal line in a semiconductor device according to claim 7 , wherein the insulating film is etched by means of a dry etching process using activated plasma comprising a combination of CHF 3 /CF 4 /Ar or C x F y (where x, y are natural numbers)/O 2 /Ar gas.

12. A method of forming a metal line in a semiconductor memory device according to claim 7 , wherein the third and second conductive layers are dry-etched using activated plasma comprising Cl 2 /BCl 3 /N 2 gas.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: KEY FOUNDRY CO., LTD.
Reel/Frame 053703/0227 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Recorded Nov 25, 2014
From: US BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 034469/0001 →
RELEASE OF SECURITY INTEREST Recorded Jun 22, 2010
From: U.S. BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 024563/0807 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2005
From: HYNIX SEMICONDUCTOR, INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016216/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2003
From: LEE, JOON HYEON
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 014791/0218 →