IP Library Granted Patent US 6,946,381
Granted Patent B2
US 6,946,381 · App. 10/731,487 · Granted Sep 20, 2005

Method of forming insulating film in semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,946,381
App. No.
10/731,487
Granted
Sep 20, 2005
Kind
B2
Abstract

The present invention relates to a method of forming an insulating film in a semiconductor device. The method includes forming a low dielectric constant insulating film containing a foaming agent on a semiconductor substrate, forming a contact hole or a trench in a low dielectric constant insulating film by means of a dual damascene process, and then making the low dielectric constant insulating film containing the foaming agent a porous low dielectric constant insulating film. It is therefore possible to prevent chemicals used in a dual damascene process from remaining in pores of the porous low dielectric constant insulating film. Consequently, the present invention has advantages that it can prevent metal wirings formed in a contact hole or a trench from being eroded and enhance reliability of the process and electrical properties of the device.

Claims (17)

1. A method of forming an insulating film in a semiconductor device, comprising the steps of:

forming a low dielectric constant insulating film containing a foaming agent on a semiconductor substrate in which various elements for forming the semiconductor device are formed;

forming a dual damascene pattern in the low dielectric constant insulating film; and

performing an annealing process so that the foaming agent reacts with the low dielectric constant insulating film to form pores therein, thus making the low dielectric constant insulating film a porous low dielectric constant insulating film,

wherein the pores are formed after the damascene pattern is formed so that it is possible to prevent chemicals used in the step of forming the dual damascene pattern from remaining in the pores of the porous low dielectric constant insulating film.

2. The method as claimed in claim 1 , wherein poly methyl metacrylate (PMMA) copolymer, and high polymer having aliphatic or aromatic core are used as the foaming agent.

3. The method as claimed in claim 1 , wherein methyl silsesquioxane (MSSQ) is used as a matrix of the low dielectric constant insulating film.

4. The method as claimed in claim 1 , wherein the process of forming the dual damascene pattern is performed at a temperature of −50° C. to room temperature.

5. The method as claimed in claim 1 , wherein the annealing process is performed at a temperature in the range of 200° C. to 500° C.

6. A method of forming an insulating film in a semiconductor device, comprising the steps of:

forming a low dielectric constant insulating film containing a foaming agent on a semiconductor substrate in which various elements for forming the semiconductor device are formed;

forming a dual damascene pattern in the low dielectric constant insulating film; and

subsequently performing an annealing process so that the foaming agent reacts with the low dielectric constant insulating film to form pores therein, thus making the low dielectric constant insulating film a porous low dielectric constant insulating film.

7. The method as claimed in claim 6 , wherein polypoly methyl metacrylate (PMMA) copolymer, and high polymer having aliphatic or aromatic core are used as the foaming agent.

8. The method as claimed in claim 6 , wherein methyl silsesquioxane (MSSQ) is used as a matrix of the low dielectric constant insulating film.

9. The method as claimed in claim 6 , wherein the process of forming the dual damascene pattern is performed at a temperature of −50° C. to room temperature.

10. The method as claimed in claim 6 , wherein the annealing process is performed at a temperature in the range of 200° C. to 500° C.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: KEY FOUNDRY CO., LTD.
Reel/Frame 053703/0227 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Recorded Nov 25, 2014
From: US BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 034469/0001 →
RELEASE OF SECURITY INTEREST Recorded Jun 22, 2010
From: U.S. BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 024563/0807 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2005
From: HYNIX SEMICONDUCTOR, INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016216/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2003
From: HWANG, SUNG BO
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 014786/0689 →