IP Library Granted Patent US 7,183,218
Granted Patent B2
US 7,183,218 · App. 10/734,818 · Granted Feb 27, 2007

Methods for fabricating a semiconductor device with etch end point detection

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Quick Facts
Patent No.
US 7,183,218
App. No.
10/734,818
Granted
Feb 27, 2007
Kind
B2
Abstract

The present invention relates to a fabrication method of a semiconductor device using EPD system, which enables uniform hole etching regardless of changes of etch rates of etching chemical and thickness of interlayer insulating layer after CMP, and the fabrication method comprises: forming a nitride layer on an interlayer insulating layer; forming a photoresist layer on the nitride layer, and exposing and developing the photoresist layer to form a photoresist pattern; etching the nitride layer using the photoresist pattern as a mask and contiguously etching the photoresist pattern and the interlayer insulating layer together; setting etch stop point as the point that the photoresist pattern is removed by etching and thus the nitride layer is exposed.

Claims (35)

1. A method to fabricate a semiconductor device comprising:

forming a nitride layer on an interlayer insulating layer;

forming a photoresist layer on the nitride layer;

forming a photoresist pattern from the photoresist layer, the photoresist pattern having a thickness that depends on a thickness and an etch rate of the interlayer insulating layer and an etch rate of the photoresist pattern;

etching the nitride layer using the photoresist pattern as a mask;

etching the interlayer insulating layer together with the photoresist pattern; and

setting an etch stop point as a point at which the photoresist pattern is removed by etching.

2. A method as defined in claim 1 , wherein the nitride layer has a thickness of approximately 200–800 Å.

3. A method as defined in claim 1 , wherein the photoresist pattern has a thickness of approximately 2500–3500 Å.

4. A method as defined in claim 1 , further comprising, after the photoresist pattern is removed, over-etching the interlayer insulating layer using the nitride layer as a mask.

5. A method to fabricate a semiconductor device comprising:

forming a first mask layer on an etch target layer;

forming a second mask layer on the first mask layer;

forming a first mask pattern by selectively etching the second mask layer, the first mask pattern having a thickness that depends on a thickness and an etch rate of the etch target layer and an etch rate of the first mask pattern;

forming a second mask pattern by etching to first mask layer using the first mask pattern as a mask;

etching the etch target layer together with the first mask pattern, wherein the first mask pattern is etched using the second mask pattern as a mask; and

setting an etch stop point as a point at which the first mask pattern is removed by etching.

6. A method as defined in claim 5 , wherein the first mask layer and the etch target layer have a same etch rate.

7. A method as defined in claim 5 , wherein the first mask layer and the etch target layer have a different etch rate.

8. A method as defined in claim 6 , wherein a thickness or the first mask layer is further determined by a desired etch depth in the etch target layer.

9. A method as defined in claim 8 , wherein the first mask layer comprises a same material as the etch target layer.

10. A method to fabricate a semiconductor device comprising:

forming a nitride layer on an interlayer insulating layer;

forming a photoresist layer on the nitride layer;

forming a photoresist pattern from the photoresist layer, the photoresist pattern having a thickness that depends on a thickness and an etch rate of the interlayer insulating layer and an etch rate of photoresist pattern;

etching the nitride layer using the photoresist pattern as a mask;

etching the interlayer insulating layer together with the photoresist pattern; and

setting an etch stop point as a point at which the nitride layer is exposed.

11. A method to fabricate a semiconductor device comprising:

forming a first mask layer on an etch target layer;

forming a second mask layer on the first mask layer;

forming a first mask pattern by selectively etching the second mask layer, the first mask pattern having a thickness that depends on a thickness and an etch rate of the etch target layer and an etch rate of first mask pattern;

forming a second mask pattern by etching to first mask layer using the first mask pattern as a mask;

etching the etch target layer together with the first mask pattern, wherein the first mask pattern is etched using the second mask pattern as a mask; and

setting an etch stop point as a point at which the second mask pattern is exposed.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017749 FRAME 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.". Recorded Jun 21, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017821/0670 →
CHANGE OF NAME Recorded Jun 8, 2006
From: DONGANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017749/0335 →
MERGER Recorded May 31, 2005
From: ANAM SEMICONDUCTOR INC.; ANAM SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR, INC., A KOREAN CORPORATION
Reel/Frame 016593/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2004
From: LEE, DATE-GUN
To: ANAM SEMICONDUCTOR INC.
Reel/Frame 015146/0236 →