Redundant single event upset supression system
CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.
1. A system comprising:
transistors adapted to operate as an SR flip-flop wherein each one of the transistors has an insulated gate and wherein the SR flip-flop is a SEUSSNor comprising:
a power node and four p type transistors named P 2 , P 4 , P 6 , and P 8 wherein the sources of P 2 , P 4 , P 6 , and P 8 are connected to the power node;
a ground node and eight n type transistors named N 1 , N 2 , N 3 , N 4 , N 5 , N 6 , N 7 , and N 8 wherein the sources of N 1 , N 2 , N 3 , N 4 , N 5 , N 6 , N 7 , and N 8 are connected to the ground node;
a p type transistor called P 1 wherein the source of P 1 is connected to the drain of P 2 ;
a p type transistor called P 3 wherein the source of P 3 is connected to the drain of P 4 ;
a p type transistor called P 5 wherein the source of P 5 is connected to the drain of P 6 ;
a p type transistor called P 7 wherein the source of P 7 is connected to the drain of P 8 ;
an S input connected to the gate of P 1 , the gate of N 1 , the gate of N 5 and the gate of P 5 ;
an R input connected to the gate of P 3 , the gate of N 3 , the gate of N 7 and the gate of P 7 ;
a Q 2 node connected to the gate of P 2 , the gate of N 6 , the drain of N 7 , the drain of P 7 , and the drain of N 8 ;
a Qbar node connected to the gate of P 4 , the gate of N 8 , the drain of N 1 , the drain of P 1 , and the drain of N 2 ;
a Q node connected to the gate of P 6 , the gate of N 2 , the drain of N 3 , the drain of P 3 , and the drain of N 4 ; and
a Qbar 2 node connected to the gate of P 8 , the gate of N 4 , the drain of N 5 , the drain of P 5 , and the drain of N 6 .
2. The system of claim 1 further comprising at least two more SR flip flops and a voting circuit such that the circuit output is the majority output of all of the SR flip-flops.
3. The system of claim 1 further comprising:
a two input NAND gate called G 1 wherein the first input of G 1 is connected to a TRed 2 R input node and the output of G 1 is connected to the S input;
a two input NAND gate called G 2 wherein the first input of G 2 is connected to a TRed 2 S input node and the output of G 2 is connected to the second input of G 1 ;
a two input NAND gate called G 3 wherein the first input of G 3 is connected to the TRed 2 S input node and the output of G 3 is connected to the R input;
a two input NAND gate called G 4 wherein the first input of G 4 is connected to the TRed 2 R input node and the output of G 4 is connected to the second input of G 3 ;
an SR flip-flop called SR 2 wherein the S input of SR 2 is connected to the output of G 1 and the R input of SR 2 is connected to the output of G 3 ;
an SR flip-flop called SR 3 wherein the S input of SR 3 is connected to the output of G 1 and the R input of SR 3 is connected to the output of G 3 ;
a three input NAND gate called G 5 wherein the first input of G 5 is connected to either the Q node or the Q 2 node, the second input of G 5 is connected to the Q output of SR 2 , and the third input of G 5 is connected to the Q output of SR 3 ;
a three input NAND gate called G 6 wherein the first input of G 6 is connected to either the Qbar node or the Qbar 2 node, the second input of G 6 is connected to the Qbar output of SR 2 , and the third input of G 6 is connected to the Qbar output of SR 3 ;
a two input NAND gate called G 7 wherein the first input of G 7 is connected to either the Q node or the Q 2 node and the second input of G 7 is connected to the Q output of SR 2 ;
a two input NAND gate called G 8 wherein the first input of G 8 is connected to either the Q node or the Q 2 node and the second input of G 8 is connected to the Q output of SR 3 ;
a two input NAND gate called G 9 wherein the first input of G 9 is connected to the Q output of SR 2 and the second input of G 9 is connected to the Q output of SR 3 ;
a three input NAND gate called G 10 wherein the first input of G 10 is connected to the output of G 7 , the second input of G 10 is connected to the output of G 8 , the third input of G 10 is connected to the output of G 9 , and the output of G 10 is connected to a TRed 2 Q output node;
an inverter called I 1 wherein the input of I 1 is connected to the TRed 2 Q output node and the output of I 1 is connected to a TRed 2 Qbar output node;
a two input NAND gate called G 11 wherein the first input of G 11 is connected to the output of G 5 and the second input of G 11 is connected to the output of G 10 and the output of G 11 is connected to the second input of G 4 ; and
a two input NAND gate called G 12 wherein the first input of G 12 is connected to the output of G 6 and the second input of G 12 is connected to the output of I 1 and the output of G 12 is connected to the second input of G 2 .
4. The system of claim 1 further comprising at least two more SR flip flops and a correction circuit such that the circuit output is the corrected output of all of the SR flip-flops.
5. The system of claim 1 further comprising:
a two input NAND gate called G 1 wherein the first input of G 1 is connected to a TRed 1 R input node and the output of G 1 is connected to the S input;
a two input NAND gate called G 2 wherein the first input of G 2 is connected to a TRed 1 S input node and the output of G 2 is connected to the second input of G 1 ;
a two input NAND gate called G 3 wherein the first input of G 3 is connected to the TRed 1 S input node and the output of G 3 is connected to the R input;
a two input NAND gate called G 4 wherein the first input of G 4 is connected to the TRed 1 R input node and the output of G 4 is connected to the second input of G 3 ;
an SR flip-flop called SR 2 wherein the S input of SR 2 is connected to the output of G 1 and the R input of SR 2 is connected to the output of G 3 ;
an SR flip-flop called SR 3 wherein the S input of SR 3 is connected to the output of G 1 and the R input of SR 3 is connected to the output of G 3 ;
a TRed 1 Q node connected to either the Q node or the Q 2 node;
a TRed 1 Qbar node connected to either the Qbar node or the Qbar 2 node;
a two input NAND gate called G 11 wherein the first input of G 11 is connected to the Q output of SR 2 and the second input of G 11 is connected to the Q output of SR 3 ;
a two input NAND gate called G 12 wherein the first input of G 12 is connected to the Qbar output of SR 2 and the second input of G 12 is connected to the Qbar output of SR 3 ;
a two input NAND gate called G 13 wherein the first input of G 13 is connected to the output of G 11 and the second input of G 13 is connected to the output of G 12 ;
a two input NAND gate called G 5 wherein the first input of G 5 is connected to the TRed 1 Q node and the second input of G 5 is connected to the output of G 13 ;
a two input NAND gate called G 6 wherein the first input of G 6 is connected to the TRed 1 Qbar node and the second input of G 6 is connected to the output of G 11 ;
a two input NAND gate called G 7 wherein the first input of G 7 is connected to the output of G 5 , the second input of G 7 is connected to the output of G 6 and the output of G 7 is connected to the second input of G 2 ;
a two input NAND gate called G 8 wherein the first input of G 8 is connected to the TRed 1 Qbar node and the second input of G 8 is connected to the output of G 13 ;
a two input NAND gate called G 9 wherein the first input of G 9 is connected to the TRed 1 Q node and the second input of G 9 is connected to the output of G 12 ; and
a two input NAND gate called G 10 wherein the first input of G 10 is connected to the output of G 8 , the second input of G 10 is connected to the output of G 9 and the output of G 10 is connected to the second input of G 4 .
6. A system comprising:
transistors adapted to operate as an SR flip-flop wherein each one of the transistors comprises has an insulated gate and wherein the SR flip-flop is a SEUSSNand comprising:
a power node and eight p type transistors named P 1 , P 2 , P 3 , P 4 , P 5 , P 6 , P 7 , and P 8 wherein the sources of P 1 , P 2 , P 3 , P 4 , P 5 , P 6 , P 7 , and P 8 are connected to the power node;
a ground node and four n type transistors named N 2 , N 4 , N 6 , and N 8 wherein the sources of N 2 , N 4 , N 6 , and N 8 are connected to the ground node;
an n type transistor called N 1 wherein the source of N 1 is connected to the drain of N 2 ;
an n type transistor called N 3 wherein the source of N 3 is connected to the drain of N 4 ;
an n type transistor called N 5 wherein the source of N 5 is connected to the drain of N 6 ;
an n type transistor called N 7 wherein the source of N 7 is connected to the drain of N 8 ;
an S input connected to the gate of P 1 , the gate of N 1 , the gate of N 5 and the gate of P 5 ;
an R input connected to the gate of P 3 , the gate of N 3 , the gate of N 7 and the gate of P 7 ;
a Qbar 2 node connected to the gate of P 2 , the gate of N 6 , the drain of P 7 , the drain of N 7 , and the drain of P 8 ;
a Q node connected to the gate of P 4 , the gate of N 8 , the drain of N 1 , the drain of P 1 , and the drain of P 2 ;
a Qbar node connected to the gate of P 6 , the gate of N 2 , the drain of N 3 , the drain of P 3 , and the drain of P 4 ; and
a Q 2 output node connected to the gate of P 8 , the gate of N 4 , the drain of N 5 , the drain of P 5 , and the drain of P 6 .
7. The system of claim 6 further comprising at least two more SR flip flops and a voting circuit such that the circuit output is the majority output of all of the SR flip-flops.
8. The system of claim 6 further comprising:
a two input NAND gate called G 1 wherein the first input of G 1 is connected to a TRed 2 R input node and the output of G 1 is connected to the S input;
a two input NAND gate called G 2 wherein the first input of G 2 is connected to a TRed 2 S input node and the output of G 2 is connected to the second input of G 1 ;
a two input NAND gate called G 3 wherein the first input of G 3 is connected to the TRed 2 S input node and the output of G 3 is connected to the R input;
a two input NAND gate called G 4 wherein the first input of G 4 is connected to the TRed 2 R input node and the output of G 4 is connected to the second input of G 3 ;
an SR flip-flop called SR 2 wherein the S input of SR 2 is connected to the output of G 1 and the R input of SR 2 is connected to the output of G 3 ;
an SR flip-flop called SR 3 wherein the S input of SR 3 is connected to the output of G 1 and the R input of SR 3 is connected to the output of G 3 ;
a three input NAND gate called G 5 wherein the first input of G 5 is connected to either the Q node or the Q 2 output node, the second input of G 5 is connected to the Q output of SR 2 , and the third input of G 5 is connected to the Q output of SR 3 ;
a three input NAND gate called G 6 wherein the first input of G 6 is connected to either the Qbar node or the Qbar 2 node, the second input of G 6 is connected to the Qbar output of SR 2 , and the third input of G 6 is connected to the Qbar output of SR 3 ;
a two input NAND gate called G 7 wherein the first input of G 7 is connected to either the Q node or the Q 2 output node and the second input of G 7 is connected to the Q output of SR 2 ;
a two input NAND gate called G 8 wherein the first input of G 8 is connected to either the Q node or the Q 2 output node and the second input of G 8 is connected to the Q output of SR 3 ;
a two input NAND gate called G 9 wherein the first input of G 9 is connected to the Q output of SR 2 and the second input of G 9 is connected to the output of SR 3 ;
a three input NAND gate called G 10 wherein the first input of G 10 is connected to the output of G 7 , the second input of G 10 is connected to the output of G 8 , the third input of G 10 is connected to the output of G 9 , and the output of G 10 is connected to a TRed 2 Q output node;
an inverter called I 1 wherein the input of I 1 is connected to the TRed 2 Q output node and the output of I 1 is connected to a TRed 2 Qbar output node;
a two input NAND gate called G 11 wherein the first input of G 11 is connected to the output of G 5 and the second input of G 11 is connected to the output of G 10 and the output of G 11 is connected to the second input of G 4 ; and
a two input NAND gate called G 12 wherein the first input of G 12 is connected to the output of G 6 and the second input of G 12 is connected to the output of I 1 and the output of G 12 is connected to the second input of G 2 .
9. The system of claim 6 further comprising at least two more SR flip flops and a correction circuit such that the circuit output is the corrected output of all of the SR flip-flops.
10. The system of claim 6 further comprising:
a two input NAND gate called G 1 wherein the first input of G 1 is connected to a TRed 1 R input node and the output of G 1 is connected to the S input;
a two input NAND gate called G 2 wherein the first input of G 2 is connected to a TRed 1 S input node and the output of G 2 is connected to the second input of G 1 ;
a two input NAND gate called G 3 wherein the first input of G 3 is connected to the TRed 1 S input node and the output of G 3 is connected to the R input;
a two input NAND gate called G 4 wherein the first input of G 4 is connected to the TRed 1 R input node and the output of G 4 is connected to the second input of G 3 ;
an SR flip-flop called SR 2 wherein the S input of SR 2 is connected to the output of G 1 and the R input of SR 2 is connected to the output of G 3 ;
an SR flip-flop called SR 3 wherein the S input of SR 3 is connected to the output of G 1 and the R input of SR 3 is connected to the output of G 3 ;
a TRed 1 Q node connected to either the Q node or the Q 2 output node;
a TRed 1 Qbar node connected to either the Qbar node or the Qbar 2 node;
a two input NAND gate called G 11 wherein the first input of G 11 is connected to the Q output of SR 2 and the second input of G 11 is connected to the Q output of SR 3 ;
a two input NAND gate called G 12 wherein the first input of G 12 is connected to the Qbar output of SR 2 and the second input of G 12 is connected to the Qbar output of SR 3 ;
a two input NAND gate called G 13 wherein the first input of G 13 is connected to the output of G 11 and the second input of G 13 is connected to the output of G 12 ;
a two input NAND gate called G 5 wherein the first input of G 5 is connected to the TRed 1 Q node and the second input of G 5 is connected to the output of G 13 ;
a two input NAND gate called G 6 wherein the first input of G 6 is connected to the TRed 1 Qbar node and the second input of G 6 is connected to the output of G 11 ;
a two input NAND gate called G 7 wherein the first input of G 7 is connected to the output of G 5 , the second input of G 7 is connected to the output of G 6 and the output of G 7 is connected to the second input of G 2 ;
a two input NAND gate called G 8 wherein the first input of G 8 is connected to the TRed 1 Qbar node and the second input of G 8 is connected to the output of G 13 ;
a two input NAND gate called G 9 wherein the first input of G 9 is connected to the TRed 1 Q node and the second input of G 9 is connected to the output of G 12 ; and
a two input NAND gate called G 10 wherein the first input of G 10 is connected to the output of G 8 , the second input of G 10 is connected to the output of G 9 and the output of G 10 is connected to the second input of G 4 .