IP Library › Granted Patent US 6,979,588
Granted Patent B2
US 6,979,588 · App. 10/737,227 · Granted Dec 27, 2005

Method for manufacturing CMOS image sensor having microlens therein with high photosensitivity

Assignee: Hynix Semiconductor Inc.
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Quick Facts
Patent No.
US 6,979,588
App. No.
10/737,227
Granted
Dec 27, 2005
Kind
B2
Abstract

The method for manufacturing a CMOS image sensor is employed to prevent bridge phenomenon between adjacent microlenses by employing openings between the microlenses. The method includes the steps of: preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process; forming an interlayer dielectric (ILD), metal interconnections and a passivation layer formed on the semiconductor substrate in sequence; forming a color filter array having a plurality of color filters on the passivation layer; forming an over-coating layer (OCL) on the color filter array by using a positive photoresist or a negative photoresist; forming openings in the OCL by patterning the OCL by using a predetermined mask; and forming dome-typed microlenses on a patterned OCL.

Claims (47)

1. A method for manufacturing a complementary metal oxide semiconductor (CMOS) image sensor having microlenses therein, the method comprising the steps of:

a) preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process;

b) forming an interlayer dielectric (ILD), metal interconnections and a passivation layer formed on the semiconductor substrate in sequence;

c) forming a color filter array having a plurality of color filters on the passivation layer;

d) forming an over-coating layer (OCL) on the color filter array by using a positive photoresist;

e) forming openings in the OCL by patterning the OCL by using a binary mask, wherein the binary mask has coated portions and uncoated portions, the uncoated portions being disposed above boundaries between the color filters; and

f) forming dome-typed microlenses on a patterned OCL.

2. The method as recited in claim 1 , wherein the step f) includes the steps of:

f1) forming a microlens layer on the patterned OCL;

f2) forming rectangular microlenses by patterning the microlens layer into a predetermined configuration; and

f3) carrying out a flow process.

3. The method as recited in claim 2 , wherein the microlens layer uses a silicon oxide-based photoresist material.

4. The method as recited in claim 1 , wherein the uncoated portion of the binary mask has the width less than a maximum resolution in order to form the opening with the width in the range of about 0.1 μm to about 0.2 μm.

5. The method as recited in claim 1 , wherein the width and the height of the opening is adjusted by controlling a dose amount.

6. The method as recited in claim 1 , wherein the coated portions of the binary mask are coated with chromium (Cr).

7. The method as recited in claim 1 , after the step d), further comprising the step of carrying out a curing process for hardening the OCL.

8. A method for manufacturing a CMOS image sensor having microlenses therein, the method comprising the steps of:

a) preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process;

b) forming an ILD, metal interconnections and a passivation layer formed on the semiconductor substrate in sequence;

c) forming a color filter array having a plurality of color filters on the passivation layer;

d) forming an OCL on the color filter array by using a negative photoresist;

e) forming openings in the OCL by patterning the OCL by using a binary mask, wherein the binary mask has coated portions and uncoated portions, the coated portions being disposed above boundaries between the color filters; and

f) forming dome-typed microlenses on a patterned OCL.

9. The method as recited in claim 8 , the step f) includes the steps of:

f1) forming a microlens layer on the patterned OCL;

f2) forming rectangular microlenses by patterning the microlens layer into a predetermined configuration; and

f3) carrying out a flow process.

10. The method as recited in claim 9 , wherein the microlens layer uses a silicon oxide-based photoresist material.

11. The method as recited in claim 8 , wherein the coated portion of the binary mask has the width less than a maximum resolution in order to form the opening with the width in the range of about 0.1 μm to about 0.2 μm.

12. The method as recited in claim 8 , wherein the width and the height of the opening is adjusted by controlling a dose amount.

13. The method as recited in claim 8 , wherein the coated portions of the binary mask are coated with Cr.

14. The method as recited in claim 8 , after the step d), further comprising the step of carrying out a curing process for hardening the OCL.

15. A method for manufacturing a CMOS image sensor having microlenses therein, the method comprising the steps of:

a) preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process;

b) forming an ILD, metal interconnections and a passivation layer formed on the semiconductor substrate in sequence;

c) forming a color filter array having a plurality of color filters on the passivation layer;

d) forming an OCL on the color filter array by using a negative photoresist;

e) forming openings in the OCL by patterning the OCL by using a phase shifted mask (PSM), wherein the PSM has a 0° phase and a 180° phase, boundaries between the 0° phase and the 180° phase being disposed above boundaries between the color filters; and

f) forming dome-typed microlenses on a patterned OCL.

16. The method as recited in claim 15 , the step f) includes the steps of:

f1) forming a microlens layer on the patterned OCL;

f2) forming rectangular microlenses by patterning the microlens layer into a predetermined configuration; and

f3) carrying out a flow process.

17. The method as recited in claim 16 , wherein the microlens layer uses a silicon oxide-based photoresist material.

18. The method as recited in claim 15 , wherein each opening has the width ranging from about 0.03 μm to about 0.1 μm.

19. The method as recited in claim 15 , wherein the width and the height of the opening is adjusted by controlling a dose amount.

20. The method as recited in claim 15 , after the step d), further comprising the step of carrying out a curing process for hardening the OCL.

Assignments (6)
MERGER Recorded Jul 22, 2011
From: CROSSTEK CAPITAL, LLC
To: INTELLECTUAL VENTURES II LLC
Reel/Frame 026637/0632 →
PARTIAL RELEASE OF SECURITY INTEREST Recorded Aug 10, 2009
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 023075/0054 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: CROSSTEK CAPITAL, LLC
Reel/Frame 022764/0270 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2005
From: HYNIX SEMICONDUCTOR, INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016216/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2003
From: JEONG, CHANG-YOUNG; SHIN, DAE-UNG; KIM, HONG-IK
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 014812/0158 →
Priority Claims (2)
KR 10-2003-0005765 · Jan 29, 2003 · national
KR 10-2003-0027019 · Apr 29, 2003 · national
Continuity (1)
Related Publication 20040147059A1 · Jul 29, 2004