Systems and methods for testing receiver terminations in integrated circuits

1. A method for testing an integrated circuit (IC), the IC having a first pad configured as a signal interface for components external to the IC, the first pad having a receiver configured to receive an input signal from a component external to the IC, said method comprising:

electrically interconnecting automated test equipment (ATE) with the IC;

providing at least one stimulus to the IC such that the IC measures a receiver termination characteristic of the first pad; and

receiving information corresponding to the receiver termination characteristic of the first pad.

2. The method of claim 1 , wherein the receiver has at least a first P-type transistor and at least a first N-type transistor, and the IC has at least one other N-type transistor; and

further comprising:

disabling the first N-type transistor of the receiver;

activating at least the first P-type transistor of the receiver;

activating at least the other N-type transistor of the IC; and

determining whether an output of at least the first P-type transistor is greater than an output of at least the other N-type transistor.

3. The method of claim 2 , wherein the IC has at least one other P-type transistor; and

further comprising:

disabling the first P-type transistor of the receiver;

activating at least the first N-type transistor of the receiver;

activating at least the other P-type transistor the IC: and

determining whether an output of a least the first N-type transistor is greater than an output of at least the other P-type transistor.

4. The method of claim 2 , wherein multiple iterations of the determining are performed using different combinations of P-type and N-type transistors.

5. The method of claim 1 , wherein the IC has a second pad; and

wherein providing at least one stimulus comprises:

electrically interconnecting the first pad with a second pad of the IC; and

providing the at least one stimulus such that the IC measures a receiver termination characteristic of the second pad.

6. The method of claim 1 , wherein the IC includes a scan register; and

wherein the information received is captured by the scan register.

7. The method of claim 1 , wherein providing at least one stimulus comprises:

providing the at least one stimulus from the ATE.

8. The method of claim 1 , wherein the IC has a plurality of pads, and wherein electrically interconnecting automated test equipment (ATE) with the IC comprises electrically interconnecting the ATE to a subset of the plurality of pads.

9. The method of claim 1 , wherein the first pad has a driver configured to provide an output signal to a component external to the IC.

10. The method of claim 9 , further comprising:

measuring driver strength of the first pad at the IC in response to the at least one stimulus.

11. An integrated circuit (IC) comprising:

a first pad electrically communicating with at least a portion of said IC, said first pad having a first receiver configured to receive a first pad input signal from a component external to said IC and to provide, to a component internal to said IC, a first receiver digital output signal in response to the first pad input signal; and

a first test circuit internal to said IC and being adapted to provide information corresponding to a receiver termination characteristic of the first pad.

12. The IC of claim 11 , wherein:

the receiver has at least a first P-type transistor and at least a first N-type transistor;

the IC has at least one other N-type transistor; and

the first test circuit is operative to:

disable the first N-type transistor of the receiver;

activate at least the first P-type transistor of the receiver;

activate at least the other N-type transistor of the IC; and

determine whether an output of at least the first P-type transistor is greater than an output of at least the other N-type transistor.

13. The IC of claim 11 , wherein:

the receiver has at least a first N-type transistor and at least a first P-type transistor;

the IC has at least one other P-type transistor; and

the first test circuit is operative to:

disable the first P-type transistor of the receiver;

activate at least the first N-type transistor of the receiver;

activate at least the other P-type transistor of the IC; and

determine whether an output of at least the first N-type transistor is greater than an output of at least the other P-type transistor.

14. The IC of claim 11 , further comprising a scan register electrically communicating with the receiver and operative to capture the output of the receiver.

15. The IC of claim 11 , wherein the first pad has a driver configured to provide an output signal to a component external to the IC.

16. The IC of claim 15 , wherein the first test circuit is operative to measure driver strength of the first pad at the IC.

17. An integrated circuit (IC) comprising:

a first pad electrically communicating with at least a portion of said IC, said first pad having a first receiver configured to receive a first pad input signal from a component external to said IC and to provide, to a component internal to said IC, a first receiver digital output signal in response to said first pad input signal; and

means for providing information corresponding to a receiver termination characteristic of the first pad.

18. A system for testing an integrated circuit, said system comprising:

automated test equipment (ATE) configured to electrically interconnect with an IC and to provide at least one stimulus to the IC; and

an integrated circuit (IC) having a first pad, said first pad having a first receiver and a first test circuit, said first receiver being configured to receive a first pad input signal from said ATE and to provide, to a component internal to said IC, a first receiver digital output signal in response to said first pad input signal, said first test circuit being configured to electrically communicate with said ATE such that, in response to receiving said at least one stimulus from said ATE, said first test circuit provides information, corresponding to a receiver termination characteristic of said first receiver of said first pad, to said ATE.

19. The system of claim 18 , wherein said IC has a plurality of pads, said ATE is configured to electrically interconnect with a subset of said plurality of pads, and said system is configured to measure a receiver termination characteristic of each receiver of each of said plurality of pads while said ATE is electrically interconnected with said subset of pads.

20. The system of claim 18 , wherein:

the first pad has a driver configured to provide an output signal to a component external to the IC; and

the first test circuit is operative to measure driver strength of the first pad at the IC.