IP Library Granted Patent US 6,999,343
Granted Patent B2
US 6,999,343 · App. 10/738,235 · Granted Feb 14, 2006

Method of programming a flash memory cell and method of programming an NAND flash memory using the same

Assignee: Hynix Semiconductor Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,999,343
App. No.
10/738,235
Granted
Feb 14, 2006
Kind
B2
Abstract

The disclosed is a method of programming a flash memory cell, comprising; a step of an over-programming of a flash memory cell to-be-programmed; a first recovering step of the over-programmed flash memory cell by adjusting a gate bias of the flash memory cell; a second recovering step of the over-programmed flash memory cell by setting the gate bias to a voltage of 0V and then adjusting a bulk bias of the over-programmed flash memory cell; a third recovering step of the over-programmed flash memory cell by floating the gate bias and then adjusting the bulk bias of the over-programmed flash memory cell; and a fourth recovering step of the over-programmed flash memory cell by adjusting the bulk bias of the over-programmed flash memory cell using a self-boosting operation.

Claims (19)

1. A method of programming a flash memory cell, comprising;

a step of an over-programming of a flash memory cell to-be-programmed;

a first recovering step of the over-programmed flash memory cell by adjusting a gate bias of the flash memory cell;

a second recovering step of the over-programmed flash memory cell by setting the gate bias to a voltage of 0V and then adjusting a bulk bias of the over-programmed flash memory cell;

a third recovering step of the over-programmed flash memory cell by floating the gate bias and then adjusting the bulk bias of the over-programmed flash memory cell; and

a fourth recovering step of the over-programmed flash memory cell by adjusting the bulk bias of the over-programmed flash memory cell using a self-boosting operation.

2. The method of programming a flash memory cell according to claim 1 , wherein the voltage of about 20V is applied to the gate of the flash memory cell during the over-programming step.

3. The method of programming a flash memory cell according to claim 1 , wherein the voltage of about 8V is applied to the gate of the flash memory cell during the over-programming step.

4. The method of programming a flash memory cell according to claim 1 , wherein the voltage of about 12V to about 13V is applied to the bulk and the gate of the flash memory cell is grounded during the second recovering step.

5. The method of programming a flash memory cell according to claim 1 , wherein the voltage of 8V is applied to the bulk and the gate of the flash memory cell is floated during the third recovering step.

6. The programming method of a flash memory cell according to claim 1 , wherein the voltage of 12V+Vtn is applied to a drain of the flash memory cell and the voltage of 0V is applied to the gate of the flash memory cell during the fourth recovering step.

7. A method of programming an NAND flash memory, comprising:

an over-programming step of all flash memory cells connected to a selected word line W/L;

a first recovering step of the over-programmed flash memory cells by adjusting a gate bias which is applied to the word line;

a second recovering step the over-programmed flash memory cells by setting the gate bias which is applied to the word line to a voltage of 0V and then adjusting a bulk bias of the over-programmed flash memory cells;

a third recovering step of the over-programmed flash memory cells by floating the word line and then adjusting the bulk bias of the over-programmed flash memory cells;

a fourth recovering step of the over-programmed flash memory cells by adjusting the bulk bias of the over-programmed flash memory cells using a self-boosting operation;

a verifying step of whether the flash memory cells are normally programmed or not; and

a step of returning to the first recovering step or returning to the first recovering step after increasing each bias of the first to fourth recovering steps, depending on the result of the verifying step.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2014
From: SK HYNIX INC
To: INTELLECTUAL DISCOVERY CO., LTD.
Reel/Frame 032421/0488 →
CHANGE OF NAME Recorded Mar 9, 2014
From: HYNIX SEMICONDUCTOR, INC.
To: SK HYNIX INC
Reel/Frame 032421/0496 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2004
From: SHIM, SUNG BO
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 015142/0272 →
Priority Claims (1)
KR 10-2003-0019990 · Mar 31, 2003 · national
Continuity (1)
Related Publication 20040190354A1 · Sep 30, 2004