Programmable address generator
A programmable address generator comprising at least one input for receiving a first digital address of a data word in a first memory, to be converted into a second digital address of this same data word in a second memory, or conversely, comprising: at least two hierarchically interleaved counters, that can be individually parameterized for their initial offset, their increment value, and their maximum count; at least one programming register containing said parameters of each counter, these parameters depending on the addressing conversion function to be performed; and an adder of the first address with the counter results, said adder providing said second address.
1. A programmable address generator comprising at least one input for receiving a first digital address of a data word in a first memory, to be converted into a second digital address of this same data word in a second memory, or conversely, comprising:
at least two hierarchically interleaved counters, that can be individually parameterized for their initial offset, their increment value, and their maximum count;
at least one programming register containing said parameters of each counter, these parameters depending on the addressing conversion function to be performed; and
an adder of the first address with the counter results, said adder providing said second address.
2. The address generator of claim 1 , wherein the number of programmable counters ranges between 3 and 5.
3. The address generator of claim 1 , applied to video image processing.
4. The address generator of claim 1 , wherein the counters are of fractal type.
5. The address generator of claim 1 , further comprising a circuit for controlling the different counters and registers.
6. An address generator, comprising:
a first counter operable to receive a first clock, to generate a first count in response to the first clock, and to generate a second clock in response to the first count;
a second counter coupled to the first counter and operable to generate a second count in response to the second clock; and
an adder coupled to the first and second counters and operable to generate an address by combining the first and second counts.
7. The address generator of claim 6 wherein the first and second counts include respective first and second count offsets.
8. The address generator of claim 6 wherein:
the first counter is operable to alter the first count value by a first predetermined amount during each of a plurality of periods of the first clock; and
the second counter is operable to alter the second count by a second predetermined amount during each of a plurality of periods of the second clock.
9. The address generator of claim 6 wherein the first clock has a higher frequency than the second clock.
10. The address generator of claim 6 wherein the adder is further operable to receive a base address and to generate the address by combining the base address and the first and second counts.
11. The address generator of claim 6 , further comprising:
wherein the second counter is operable to generate a third clock in response to the second count; and
a third counter coupled to the second counter and to the adder and operable to generate a third count in response to the third clock; and
wherein the adder is operable to generate the address by combining the first, second, and third counts.
12. The address generator of claim 6 wherein the first counter is operable to generate the second clock when the first count has a predetermined value.
13. The address generator of claim 6 wherein the adder is operable to generate the address by summing the first and second counts.
14. A computer system, comprising:
an address bus; and
an address generator coupled to the address bus and comprising,
a first counter operable to receive a first clock, to generate a first count in response to the first clock, and to generate a second clock in response to the first count,
a second counter coupled to the first counter and operable to generate a second count in response to the second clock, and
an adder coupled to the first and second counters and operable to generate an address by combining the first and second counts.
15. A method, comprising:
generating a first count in response to a first clock;
generating a second clock in response to the first count;
generating a second count in response to the second clock; and
generating an address by combining the first and second counts.
16. The method of claim 15 wherein generating the second clock comprises generating the second clock when the first count has a predetermined value.
17. The method of claim 15 wherein:
generating the first count comprises generating the first count starting from a first count offset; and
generating the second count comprises generating the second count starting from a second count offset.
18. The method of claim 15 wherein:
generating the first count comprises periodically altering the first count by a first predetermined amount; and
generating the second count comprises periodically altering the second count by a second predetermined amount.
19. The method of claim 15 wherein generating the address comprises combining a base address and the first and second counts.
20. The method of claim 15 , further comprising:
generating a third clock in response to the second count;
generating a third count in response to the third clock; and
wherein generating the address comprises combining the first, second, and third counts.
21. The method of claim 15 wherein generating the address comprises summing the first and second counts.