SOI substrate and semiconductor integrated circuit device
View Patent ↗A semiconductor IC device includes a base substrate comprising P − -type silicon, a first P + -type silicon layer is provided on the base substrate, and an N + -type silicon layer and a second P + -type silicon layer are provided in the same layer thereon. The impurity concentration of the first P + -type silicon layer and the N + -type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N + -type silicon layer and the second P + -type silicon layer. The first P + -type silicon layer is connected to ground potential wiring GND, and the N + -type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P + -type silicon layer and the N + -type silicon layer.
1. An SOI structure comprising: a substrate comprising a first semiconductor layer of a first conductivity type disposed in said substrate, and a second semiconductor layer of a second conductivity type which is disposed in said substrate below said first semiconductor layer, an upper surface of said second semiconductor layer contacting said first semiconductor layer substantially in an entire upper surface of said second semiconductor layer; an insulating film disposed on said substrate, an upper surface of said first semiconductor layer contacting said insulating film substantially in an entire upper surface of said first semiconductor layer; a semiconductor region disposed on said insulating film; and a third semiconductor layer of a second conductivity type which is disposed in said substrate below said first and second semiconductor layers, wherein an impurity concentration of said second semiconductor layer is higher than that of said third semiconductor layer, wherein the second semiconductor layer is disposed on the entire upper surface of the third semiconductor layer, and the first semiconductor layer is disposed on the entire upper surface of the second semiconductor layer.
2. An SOI structure according to claim 1 , wherein the third semiconductor layer comprises a semiconductor having a lower impurity concentration than that in the first and second semiconductor layers.
3. An SOI structure according to claim 1 , wherein the second semiconductor layer is formed by epitaxial growth.
4. An SOI structure according to claim 1 , wherein the second semiconductor layer is formed by doping an impurity into the third semiconductor layer.
5. An SOI structure according to claim 1 , wherein the first semiconductor layer is formed by epitaxial growth.
6. An SOI structure according to claim 1 , wherein the first semiconductor layer is formed by doping an impurity into the second semiconductor layer.
7. An SOI structure according to claim 1 , wherein the first semiconductor layer has a higher impurity concentration than that of the third semiconductor layer.
8. A semiconductor integrated circuit device comprising: a substrate comprising a first semiconductor layer of a first conductivity type disposed in said substrate, and a second semiconductor layer of a second conductivity type which is disposed in said substrate below said first semiconductor layer, an upper surface of said second semiconductor layer contacting said first semiconductor layer substantially in an entire upper surface of said second semiconductor layer; a first potential being applied to the first semiconductor layer; an insulating film disposed on said substrate; an upper surface of said first semiconductor layer contacting said insulating film substantially in an entire upper surface of said first semiconductor layer; a semiconductor region disposed on the insulating film; a third semiconductor layer of a second conductivity type which is disposed in said substrate below said first and second semiconductor layers, and an integrated circuit disposed in the semiconductor region, wherein an impurity concentration of said second semiconductor layer is higher than that of said third semiconductor layer, wherein a second potential is being applied to said second semiconductor layer, wherein a decoupling capacitor is formed between said first and second semiconductor layers, wherein the second semiconductor layer is disposed on the entire upper surface of the third semiconductor layer, and the first semiconductor layer is disposed on the entire upper surface of the second semiconductor layer.
9. A semiconductor integrated circuit device according to claim 8 , further comprising a via which extends through the semiconductor region and the insulating film and which is connected to the first semiconductor layer, wherein the first potential is applied to the first semiconductor layer through the via.
10. A semiconductor integrated circuit device according to claim 8 , wherein the first potential is applied to the first semiconductor layer through the second semiconductor layer.
11. A semiconductor integrated circuit device according to claim 8 , wherein a second potential is applied to the second semiconductor layer, and a decoupling capacitor is formed between the second semiconductor layer and the first semiconductor layer.
12. A semiconductor integrated circuit device according to claim 11 , further comprising a first via which extends through the semiconductor region and the insulating film and which is connected to the first semiconductor layer, wherein the first potential is applied to the first semiconductor layer through the first via.
13. A semiconductor integrated circuit device according to claim 11 , further comprising:
a conductive contact region disposed in the same layer as the first semiconductor layer; and
a second via which extends through the semiconductor region and the insulating film and which is connected to the contact region,
wherein the second potential is applied to the second semiconductor layer through the contact region and the second via.
14. A semiconductor integrated circuit device according to claim 11 , wherein the second potential is applied to the second semiconductor layer through the back surface thereof.
15. A semiconductor integrated circuit device according to claim 8 , further comprising a first via which extends through the semiconductor region and the insulating film and which is connected to the first semiconductor layer, wherein the first potential is applied to the first semiconductor layer through the first via.
16. A semiconductor integrated circuit device according to claim 8 , further comprising a contact region of the second conductivity type disposed in the same layer as the first semiconductor layer; and
a second via which extends through the semiconductor region and the insulating film and which is connected to the contact region,
wherein the second potential is applied to the second semiconductor layer through the contact region and the second via.
17. A semiconductor integrated circuit device according to claim 8 , wherein the second potential is applied to the second semiconductor layer through the third semiconductor layer.
18. A semiconductor integrated circuit device according to claim 8 , wherein the third semiconductor layer has a lower impurity concentration than that in the first and second semiconductor layers.
19. A semiconductor integrated circuit device according to claim 8 , wherein the second semiconductor layer is formed by epitaxial growth.
20. A semiconductor integrated circuit device according to claim 8 , wherein the second semiconductor layer is formed by doping an impurity into the third semiconductor layer.
21. A semiconductor integrated circuit device according to claim 8 , wherein the first semiconductor layer is formed by epitaxial growth.
22. A semiconductor integrated circuit device according to claim 8 , wherein the first semiconductor layer is formed by doping an impurity into the third semiconductor layer.
23. A semiconductor integrated circuit device SOI according to claim 8 , wherein the first semiconductor layer has a higher impurity concentration than that of the third semiconductor layer.