Semiconductor device
View Patent ↗Disclosed is a technique capable of improving a power supply efficiency in a power supply circuit. A power MOSFET in a high side of a combined power MOSFET constituting a DC-DC converter is constituted of a horizontal MOSFET, and a power MOSFET in a low side thereof is constituted of a vertical MOSFET.
1. A semiconductor device, comprising;
a first power supply terminal supplying a first power supply potential;
a second power supply terminal supplying a second power supply potential lower than said first power supply potential;
an output terminal connected in series between said first power supply terminal and said second power supply terminal;
a first field effect transistor in which a source-drain path is connected in series between said first power supply terminal and the output terminal; and
a second field effect transistor in which a source-drain path is connected in series between said output terminal and said second power supply terminal,
wherein said first field effect transistor comprises:
a semiconductor substrate having a first main surface and a second main surface opposite to said first main surface;
a gate insulating film formed on said first main surface of said semiconductor substrate;
a gate electrode formed on said gate insulating film; and
a first and a second semiconductor regions for a source and a drain formed on said first main surface and on both end portions of said gate electrode, and
wherein said second field effect transistor comprises:
a semiconductor substrate having a first main surface and a second main surface opposite to said first main surface;
a gate insulating film formed on said first main surface;
a gate electrode formed on said gate insulating film;
a first semiconductor region for a source formed on said first main surface and formed adjacent to said gate electrode; and
a second semiconductor region for a drain formed on said second main surface.
2. The semiconductor device according to claim 1 ,
wherein a third semiconductor region for forming a channel is formed on said first main surface of said first field effect transistor and under said gate electrode, formed in the plane direction of said semiconductor substrate and formed between said semiconductor regions for the source and the drain.
3. The semiconductor device according to claim 1 ,
wherein a third semiconductor region for forming a channel, which is formed on said semiconductor substrate of said second field effect transistor in its depth direction and formed between said semiconductor regions for the source and the drain.
4. The semiconductor device according to claim 1 ,
wherein, said second field effect transistor is provided with said gate insulating film which is formed on an inner surface of a trench formed toward said second main surface from said first main surface of said semiconductor substrate, and said gate electrode is formed on said gate insulating film.
5. The semiconductor device according to claim 1 ,
wherein the source of said first field effect transistor and the drain of said second field effect transistor are joined to a common conductor to electrically connect therebetween.
6. The semiconductor device according to claim 1 ,
wherein an outer terminal electrically connected to said gate electrode and a outer terminal electrically connected to said semiconductor region for the drain are provided on a first main surface of a semiconductor chip in which said first field effect transistor is formed and an outer terminal electrically connected to said semiconductor region for the source is provided on a second main surface opposite to said first main surface.
7. The semiconductor device according to claim 1 ,
wherein said first field effect transistor is a power MOS in High side and said second field effect transistor is a power MOS in Low side.
8. The semiconductor device according to claim 4 ,
wherein a third semiconductor region for forming a channel is formed on a side surface of said gate electrode of said second field effect transistor, formed in the depth direction of said semiconductor substrate and formed between said semiconductor regions for the source and the drain.
9. The semiconductor device according to claim 5 ,
wherein said first field effect transistor and said second field effect transistor are sealed in the same sealing resin.
10. The semiconductor device according to claim 6 ,
wherein said first field effect transistor has a structure in which said semiconductor region for the source formed on said first main surface is electrically connected to said outer terminal electrically connected to said semiconductor region for the source provided on said second main surface.
11. The semiconductor device according to claim 10 ,
wherein said first field effect transistor comprises: a conductor film formed on said first main surface and electrically connected to said semiconductor region for the source; a semiconductor region formed on said semiconductor chip and functioning to electrically connect said conductor film to said outer terminal electrically connected to said semiconductor region for the source; an insulating film deposited so as to cover said gate electrode and said conductor film on said first main surface; said outer terminal provided on said insulating film and electrically connected to said gate electrode; and said outer terminal provided on said insulating film and electrically connected to said semiconductor region for the drain.
12. A semiconductor device, comprising:
a first power supply terminal supplying a first power supply potential;
a second power supply terminal supplying a second power supply potential lower than said first power supply potential;
an output terminal connected in series between said first power supply terminal and said second power supply terminal;
a first field effect transistor in which a source-drain path is connected in series between said first power supply terminal and the output terminal; and
a second field effect transistor in which a source-drain path is connected in series between said output terminal and said second power supply terminal,
wherein said first field effect transistor comprises:
a semiconductor substrate having a first main surface and a second main surface opposite to said first main surface;
a gate insulating film formed on said first main surface of said semiconductor substrate;
a gate electrode formed on said gate insulating film; and
a first and a second semiconductor regions for a source and a drain formed on said first main surface and on both end portions of said gate electrode;
a third semiconductor region for forming a channel, which is formed on said first main surface and under said gate electrode and formed between said semiconductor regions for the source and the drain; and
an outer terminal electrically connected to said gate electrode and an outer terminal electrically connected to said semiconductor region for the drain which are provided on said first main surface, and
wherein said second field effect transistor comprises:
a semiconductor substrate having a first main surface and a second main surface opposite to said first main surface;
a trench formed toward said second main surface from said first main surface of said semiconductor substrate;
a gate insulating film formed on an inner surface of said trench;
a gate electrode formed on said gate insulating film;
a first semiconductor region for a source formed on said first main surface and on both end portions of said gate electrode;
a second semiconductor region for forming a channel, which is formed on a side surface of said gate electrode and formed between said semiconductor regions for the source and the drain;
a third semiconductor region for a drain formed on said second main surface;
an outer terminal electrically connected to said gate electrode and an outer terminal electrically connected to said semiconductor region for the source, which are provided on said first main surface; and
an outer terminal electrically connected to said semiconductor region for the drain which is provided on said second main surface.
13. The semiconductor device according to claim 12 ,
wherein said first field effect transistor and said second field effect transistor are sealed in the same sealing resin.
14. The semiconductor device according to claim 13 ,
wherein outer terminal electrically connected to said semiconductor region for the source is provided on a second main surface of a semiconductor chip in which said first field effect transistor is formed.