IP Library Granted Patent US 6,984,590
Granted Patent B2
US 6,984,590 · App. 10/743,483 · Granted Jan 10, 2006

Method of manufacturing an EEPROM device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,984,590
App. No.
10/743,483
Granted
Jan 10, 2006
Kind
B2
Abstract

A method of manufacturing an EEPROM device is disclosed. An example method forms a screen oxide film on a semiconductor substrate, forms a first ion implantation mask defining a gate insulating film forming region on the screen oxide film, and performs a first ion implantation on the semiconductor substrate and the first ion implantation mask. The example method also performs a first annealing of the semiconductor substrate, removes the screen oxide film and the first ion implantation mask, and forms a gate oxide film on the semiconductor substrate. In addition, the example method forms a second ion implantation mask defining a gate insulating film forming region on the gate oxide film, performs a second ion implantation on the semiconductor substrate and the second ion implantation mask, performs a second annealing for the semiconductor substrate, removes the second ion implantation mask; and forms a tunnel oxide film on the gate oxide film.

Claims (19)

1. A method of manufacturing an EEPROM device, comprising:

forming a screen oxide film on a semiconductor substrate;

forming a first ion implantation mask defining a gate insulating film forming region on the screen oxide film;

performing a first ion implantation on the semiconductor substrate and the first ion implantation mask;

performing a first annealing of the semiconductor substrate;

removing the screen oxide film and the first ion implantation mask;

forming a gate oxide film on the semiconductor substrate;

forming a second ion implantation mask defining a gate insulating film forming region on the gate oxide film;

performing a second ion implantation on the semiconductor substrate and the second ion implantation mask;

performing a second annealing for the semiconductor substrate;

removing the second ion implantation mask; and

forming a tunnel oxide film on the gate oxide film.

2. The method of claim 1 , wherein the gate oxide film has a thickness of 50 to 300 Å.

3. The method of claim 1 , wherein the tunnel oxide film has a thickness of 50 to 100 Å.

4. The method of claim 1 , wherein the first annealing is performed at a temperature of 1000 to 1050° C. for 10 to 20 seconds.

5. The method of claim 1 , wherein the second annealing is performed at a temperature of 1050 to 1150° C. for 10 to 20 seconds.

6. The method of claim 1 , wherein the first ion implantation is performed by implanting 31P ions with an ion implantation energy of 50 to 70 KeV and dose of 2×10 13 to 2×10 14 ion/cm 2 .

7. The method of claim 1 , wherein the second ion implantation is performed by implanting 75As ions with an ion implantation energy of 60 to 85 KeV and dose of 1×10 14 to 1×10 15 ion/cm 2 .

8. The method of claim 1 , wherein the screen oxide film has a thickness of 40 to 60 Å.

Assignments (1)
CHANGE OF NAME Recorded Jun 6, 2006
From: DONGBU ANAM SEMICONDUCTORS, INC
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017718/0964 →