IP Library Granted Patent US 7,185,172
Granted Patent B1
US 7,185,172 · App. 10/743,597 · Granted Feb 27, 2007

CAM-based search engine devices having index translation capability

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Quick Facts
Patent No.
US 7,185,172
App. No.
10/743,597
Granted
Feb 27, 2007
Kind
B1
Abstract

An integrated circuit chip includes a search engine including a content addressable memory (CAM) configured to produce CAM indices responsive to search instructions provided to the search engine. The search engine further includes an index translation circuit operatively coupled to the CAM and configured to provide translation of the CAM indices to another memory space, such as from an absolute index space associated with the CAM to a memory space associated with a database within the CAM or to a memory space of a device external to the chip, such as a command source or external SRAM.

Claims (13)

1. An integrated circuit chip comprising:

a search engine including a content addressable memory (CAM) configured to produce CAM indices responsive to search instructions provided to the search engine and an index translation circuit operatively coupled to the CAM and configured to provide translation of the CAM indices, wherein the index translation circuit is configured to receive CAM indices from a second search engine device and is configurable to provide independent index mappings for respective segments of the second search machine device.

2. An integrated circuit chip comprising:

a search engine including a content addressable memory (CAM) configured to produce CAM indices responsive to search instructions provided to the search engine and an index translation circuit operatively coupled to the CAM and configured to provide translation of the CAM indices, wherein the index translation circuit is configurable to provide independent index mappings for respective segments of the CAM, wherein the index translation circuit comprises a mapping table operative to associate respective combinations of a shift factor and a base address for a database with respective CAM segment identifiers, wherein the shift factors indicate database entry size, and wherein the index translation circuit is operative to receive a CAM index, to identify a base address and a shift factor corresponding to a CAM segment identifier in the received CAM index, to concatenate the identified base address with a segment entry offset in the received CAM index, and to shift the concatenated result according to the identified shift factor to produce a database relative index corresponding to the received CAM index.

3. An integrated circuit chip comprising:

a search engine including a content addressable memory (CAM) configurable to store a plurality of databases and operative to produce CAM indices in an index space of a search machine comprising the search engine responsive to search instructions provided to the search engine and an index translation circuit operatively coupled to the CAM and configured to translate the CAM indices produced by the CAM to database relative indices, wherein the index translation circuit is configurable to provide independent index mappings for respective segments of the CAM and wherein the index translation circuit is configured to receive CAM indices from a second search machine device and is configurable to provide independent CAM index mappings for respective segments of the second search machine device.

4. An integrated circuit chip comprising:

a search engine comprising a content addressable memory (CAM) configured to produce CAM indices responsive to search instructions provided to the search engine and an index translation circuit operatively coupled to the CAM and configured to store memory entry size information and to provide translation of the CAM indices to another memory space based on the stored memory entry size information.

5. An integrated circuit chip according to claim 4 , wherein the memory entry size information comprises entry size information for a database in the CAM.

6. An integrated circuit chip according to claim 4 , wherein the memory entry size information comprises entry size information for a memory external to the chip.

7. An integrated circuit chip according to claim 4 , wherein the index translation circuit is configured to store a base address for a memory space and a shift factor indicating a data entry size for the memory space and to generate a translated address or index from a CAM index according to the base address and the shift factor.

8. An integrated circuit chip according to claim 7 , wherein the memory space comprises one of a database, a memory space associated with a command source for the search engine, and a memory space of a external memory device.

9. An integrated circuit chip according to claim 7 , wherein the shift factor further indicates a data entry size for the CAM.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2021
From: TONG, WAI CHI
To: HING NGAI COMPANY LIMITED
Reel/Frame 055644/0860 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →