IP Library Granted Patent US 6,869,871
Granted Patent B1
US 6,869,871 · App. 10/744,494 · Granted Mar 22, 2005

Method of forming metal line in semiconductor device including forming first and second zirconium films

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Quick Facts
Patent No.
US 6,869,871
App. No.
10/744,494
Granted
Mar 22, 2005
Kind
B1
Abstract

Provided is a method of forming a metal line in a semiconductor device. According to the present invention, a barrier metal layer, a Zr film, and a Cu thin film is sequentially formed in insides of a dual damascene pattern comprising via holes and trenches. Then, a Zr film is formed on the Cu thin film, and Zr is allowed to be diffused into crystal particles of Cu and interfaces between the crystal particles by carrying out a heat treatment process thereto, so that uniform Cu (Zr) bonds are formed regardless of a depth. As a result, an EM resistance characteristic of the Cu thin film even in narrower and deeper via holes can be improved, and thus reliability of process and an electrical characteristic of a device can be also improved.

Claims (29)

1. A method of forming a metal line in a semiconductor device, comprising the steps of:

forming an interlayer insulating film on a semiconductor substrate in which various elements for forming a semiconductor device are formed;

forming a dual damascene pattern in the interlayer insulating film;

forming an barrier metal layer over the entire structure including the dual damascene pattern;

forming a first Zr film on the barrier metal layer;

filling the dual damascene pattern with a conductive layer;

forming a second Zr film over the entire structure including the conductive layer;

forming a Zr compound metal layer by allowing the conductive layer to react with Zr components of the first and the second Zr films by means of a heat treatment process; and

removing the Zr compound metal layer and the barrier metal layer on the interlayer insulating film to form a metal line.

2. The method of forming a metal line in a semiconductor device according to claim 1 , wherein the barrier metal layer is formed to have a laminated structure of TaN/Ta.

3. The method of forming a metal line in a semiconductor device according to claim 2 , wherein the TaN film is formed to have a thickness of 50 Å to 150 Å, and the Ta film is formed to have a thickness of 100 Å to 300 Å.

4. The method of forming a metal line in a semiconductor device according to claim 1 , wherein the first Zr film or the second Zr film is formed using a CVD method or a PECVD method.

5. The method of forming a metal line in a semiconductor device according to claim 4 , wherein, when the first Zr film and the second Zr film are formed, Zr (N(C 2 H 5 ) 2 ) 4 or Zr (N(CH 3 ) 2 ) 4 is supplied as precursor, an inert gas such as Ar or He is supplied as a carrier gas, and H 2 gas is supplied as a reaction gas.

6. The method of forming a metal line in a semiconductor device according to claim 5 , wherein a supply amount of the precursor is set to be in the range of 30 sccm to 1000 sccm, and a supply amount of the reaction gas is set to be in the range of 100 sccm to 3000 sccm.

7. The method of forming a metal line in a semiconductor device according to claim 6 , wherein the first Zr film or the second Zr film is formed at a temperature in the range of 300° C. to 400° C., with a power of 200 W to 5000 W applied.

8. The method of forming a metal line in a semiconductor device according to claim 5 , wherein the first Zr film or the second Zr film is formed at a temperature in the range of 300° C. to 400° C., with a power of 200 W to 5000 W applied.

9. The method of forming a metal line in a semiconductor device according to claim 4 , wherein the first Zr film or the second Zr film is formed at a temperature in the range of 300° C. to 400° C., with a power of 200 W to 5000 W applied.

10. The method of forming a metal line in a semiconductor device according to claim 1 , wherein the first Zr film is formed to have a thickness in the range of 50 Å to 1000 Å.

11. The method of forming a metal line in a semiconductor device according to claim 1 , wherein the conductive layer is formed by forming a metal seed layer and then performing an electroplating method using the metal seed layer.

12. The method of forming a metal line in a semiconductor device according to claim 1 , wherein the conductive layer is formed of copper.

13. The method of forming a metal line in a semiconductor device according to claim 1 , wherein the conductive layer is formed of copper.

14. The method of forming a metal line in a semiconductor device according to claim 1 , wherein the second Zr film is formed using a physical vapor deposition method or chemical vapor deposition method.

15. The method of forming a metal line in a semiconductor device according to claim 1 , wherein the heat treatment process is carried out in an N 2 /H 2 atmosphere by using an annealing method such as a furnace annealing or an RTP.

16. The method of forming a metal line in a semiconductor device according to claim 15 , wherein a mixture ratio of the N 2 and H 2 is in the range of 5:1 to 15:1.

17. The method of forming a metal line in a semiconductor device according to claim 15 , wherein the heat treatment process is carried out at a temperature in the range of 100° C. to 300° C. for 1 to 40 minutes.

18. The method of forming a metal line in a semiconductor device according to claim 1 , wherein the heat treatment process is carried out at a temperature in the range of 100° C. to 300° C. for 1 to 40 minutes.

19. The method of forming a metal line in a semiconductor device according to claim 1 , further comprising a step of forming a capping layer over the entire structure including the metal line, after forming the metal line.

20. The method of forming a metal line in a semiconductor device according to claim 19 , wherein the capping layer is formed of SiN.

21. The method of forming a metal line in a semiconductor device according to claim 20 , wherein the SiN is formed at a temperature of 200° C. to 400° C. by using SiH 4 gas, N 2 gas, and NH 3 gas to have a thickness of 100 Å to 500 Å.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2009
From: CROSSTEK CAPITAL, LLC
To: CHUNG CHENG HOLDINGS, LLC
Reel/Frame 023085/0877 →
PARTIAL RELEASE OF SECURITY INTEREST Recorded Aug 10, 2009
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 023075/0054 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: CROSSTEK CAPITAL, LLC
Reel/Frame 022764/0270 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2005
From: HYNIX SEMICONDUCTOR, INC.
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 016216/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2004
From: CHOI, KYEONG KEUN
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 015158/0197 →