IP Library Granted Patent US 7,135,374
Granted Patent B2
US 7,135,374 · App. 10/746,381 · Granted Nov 14, 2006

MOS transistor and fabrication method thereof

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Quick Facts
Patent No.
US 7,135,374
App. No.
10/746,381
Granted
Nov 14, 2006
Kind
B2
Abstract

A method of forming a MOS transistor is disclosed. An example method forms an insulating film and a first silicon layer on a semiconductor substrate in order. The example method forms an impurity region by injecting impurity ions into a predetermined region of the first silicon layer, forms a common source line by forming a second silicon layer on the impurity region, and then injecting impurity ions into the second silicon layer. The example method also forms a gate oxide over whole surfaces of the first silicon layer and the common source line, forms side walls made of insulating film on the gate oxide film positioned at sides of the common source line, forms drain regions by injecting impurity ions into the first silicon layer being positioned at a predetermined distance from the common source line, and forms gate electrodes on sides of the side walls.

Claims (49)

1. A method of forming a MOS transistor, comprising:

forming an insulating film and a first silicon layer on a semiconductor substrate in order;

after forming the first silicon layer, forming a trench by selectively etching the first silicon layer and burying insulating material inside thereof to define remainder regions of the first silicon layer as active region of a semiconductor device;

forming an impurity region by injecting inpurity ions into a predetermined region of the first silicon layer;

forming a common source line by forming a second silicon layer on the impurity region, and then injecting impurity ions into the second silicon layer;

forming a gate oxide over whole surfaces of the first silicon layer and the common source line;

forming side walls made of insulating film on the gate oxide film positioned at sides of the common source line;

forming drain regions by injecting impurity ions into the first silicon layer being positioned at a predetermined distance from the common source line; and

forming gate electrodes on sides of the side walls.

2. The method of claim 1 , wherein the second silicon layer comprises at least one of a polysilicon layer and a silicon epitaxial layer.

3. A method of forming a MOS transistor, comprising:

forming an insulating film and a first silicon layer on a semiconductor substrate in order;

forming an impurity region by injecting impurity ions into a predetermined region of the first silicon layer by forming a victim layer on the first silicon layer, etching a portion of the victim layer to expose the first silicon layer below the portion at which a common source line is to be formed later, and then injecting impurity ions into the exposed first silicon layer to form the impurity region;

forming a common source line by forming a second silicon layer on the impurity region, and then injecting impurity ions into the second silicon layer;

forming a gate oxide over whole surfaces of the first silicon layer and the common source line;

forming side walls made of insulating film on the gate oxide film positioned at sides of the common source line;

forming drain regions by injecting impurity ions into the first silicon layer being positioned at a predetermined distance from the common source line; and

forming gate electrodes on sides of the side walls.

4. The method of claim 3 , wherein the second silicon layer comprises at least one of a polysilicon layer and a silicon epitaxial layer.

5. The method of claim 3 , further comprising the step at removing the victim layer after injecting the impurity ions into the second silicon layer.

6. The method of claim 5 , wherein the victim layer comprises a nitride film and an oxide film in order.

7. The method of claim 6 , wherein removing the victim layer comprises wet etching the oxide film and the nitride film in order.

8. A method of forming a MOS transistor, comprising:

forming an insulating film and a first silicon layer on a semiconductor substrate in order;

forming an impurity region by injecting ions into a predetermined region of the first silicon layer;

forming a common source line by forming a second silicon layer on the impurity region, and then injecting impurity ions into the second silicon layer;

forming a gate oxide over whole surfaces of the first silicon layer and the common source line;

forming a nitride film on the gate oxide, and then etching the nitride film until the gate oxide on a top surface of the common source line is exposed to form side walls at sides of the common source line;

forming drain regions by injecting impurity ions into the first silicon layer being positioned at a predetermined distance from the common source line; and

forming gate electrodes on sides of the side walls.

9. The method of claim 8 , wherein the second silicon layer comprises at least one of a polysilicon layer and a silicon epitaxial layer.

10. A method of forming a MOS transistor, comprising:

forming an insulating film and a first silicon layer on a semiconductor substrate in order;

forming an impurity region by injecting impurity ions into a predetermined region of the first silicon layer;

forming a common source line by forming a second silicon layer on the impurity region, and then injecting impurity ions into the second silicon layer;

forming a gate oxide over whole surfaces of the first silicon layer and the common source line;

forming side walls made of insulating film on the gate oxide film positioned at sides of the common source line;

forming drain regions by forming a masking film on the gate oxide and the side walls, the masking film covering the common source line and having a larger width than the common source line, and then injecting impurity ions into the first silicon layer a predetermined distance from the common source line using the masking film as a mask; and

forming gate electrodes on sides of the side walls.

11. The method of claim 10 , wherein the second silicon layer comprises at least one of a polysilicon layer and a silicon epitaxial layer.

12. A method of forming a MOS transistor, comprising:

forming an insulating film and a first silicon layer on a semiconductor substrate in order;

forming an impurity region by injecting impurity ions into a predetermined region of the first silicon layer;

forming a common source line by forming a second silicon layer on the impurity region, and then injecting impurity ions into the second silicon layer;

forming a gate oxide over whole surfaces of the first silicon layer and the common source line;

forming side walls made of insulating film on the gate oxide film positioned at sides of the common source line;

forming drain regions by injecting impurity ions into the first silicon layer being positioned at a predetermined distance from the common source line; and

forming gate electrodes on sides of the side walls by forming a polysilicon layer and a nitride layer in order over whole surfaces of the gate oxide and the side walls, etching back the nitride film and the polysilicon layer until the gate oxide on a top surface of the common source line is exposed, thereby making the nitride film and the polysilicon layer on sides of the side walls remain, and then removing the remainder nitride film using wet etching.

13. The method of claim 12 , wherein the second silicon layer comprises at least one of a polysilicon layer and a silicon epitaxial layer.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017749 FRAME 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.". Recorded Jun 21, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017821/0670 →
CHANGE OF NAME Recorded Jun 8, 2006
From: DONGANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017749/0335 →
MERGER Recorded May 31, 2005
From: ANAM SEMICONDUCTOR INC.; ANAM SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR, INC., A KOREAN CORPORATION
Reel/Frame 016593/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2004
From: KOH, KWAN-JU
To: ANAM SEMICONDUCTOR INC.
Reel/Frame 014961/0808 →