Method for operating a memory device
View Patent ↗A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.
1. A method of operating a set of memory cells in a memory array, the method comprising:
applying a first operating pulse to a terminal of a first cell, wherein the first operating pulse is intended to place the first cell into a predefined state; and
applying a second operating pulse to a terminal of a second cell,
wherein the second operating pulse is intended to place the second cell to the predefined state, and
wherein the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.
2. The method according to claim 1 , further comprising a step of applying a third operating pulse to a terminal of a third cell,
wherein the third operating pulse is intended to place the third cell to said predefined state, and
wherein the pulse characteristics of the third pulse are a function of the response of the first and the second cells to the first and the second operating pulses, respectively.
3. The method according to claim 1 , wherein said pulse characteristics of the second operating pulse are adjusted by adjusting the duration of the second operation pulse.
4. The method according to claim 1 , wherein said pulse characteristics of the second operation pulse are adjusted by adjusting the amplitude of said second operation pulse.