Flash memory and fabrication method thereof
View Patent ↗A flash memory and a fabrication method thereof, which is capable of improving a whole capacitance of the flash memory by forming a tunneling oxide and a floating gate only in a portion where injection of electrons occurs. A flash memory wherein a tunneling oxide and a floating gate are formed only in a portion where injection of electrons occurs and a gate insulation film is formed on a semiconductor substrate between two portions of the tunneling oxide.
1. A method for fabricating a flash memory, comprising the steps of:
forming a tunneling oxide layer on a semiconductor substrate;
forming a floating gate by depositing a first polycrystalline silicon layer on the tunneling oxide layer;
selectively etching the floating gate and the tunneling oxide layer to form two regions, wherein the two regions have a predetermined width on an active area of the semiconductor substrate, are separated from each other by a predetermined interval, and are connected to each other in a field area of the semiconductor substrate;
forming a gate insulation film on the entire surface of the semiconductor substrate including the floating gate;
forming a control gate by depositing a second polycrystalline silicon layer on the gate insulation film;
exposing an outside wall of the floating gate by etching the gate insulation film formed on the outside wall of the floating gate while selectively etching the control gate and the gate insulation film such that the control gate and the gate insulation film to have a predetermined width;
forming a nitride film on the entire top surface of the semiconductor substrate and then forming a side wall on outside walls of the control gate, the gate insulation film, the floating gate, and the tunneling oxide by blanket-etching the nitride film, wherein the side wall is formed to have a height which is not greater than a height of the control gate; and
forming a source and drain region by injecting impurities into the semiconductor to the outside of the floating gate.
2. The method of claim 1 wherein, the first polycrystalline silicon and the second polycrystalline silicon are formed to have a thickness of about 2,000-3,000 Å.
3. The method of claim 1 wherein, forming the gate insulation film comprises forming the gate insulation film to be a three-layered structure of lower oxide film-nitride film-upper oxide film (ONO) by forming a lower oxide film on the floating gate by thermally oxidizing the first polycrystalline silicon layer constituting the floating gate, forming a silicon nitride film on the lower oxide film by using a thermal process, and then forming and annealing an upper oxide film on the silicon nitride film by using a thermal process.
4. The method of claim 2 wherein, forming the gate insulation film comprises forming the gate insulation film to be a three-layered structure of lower oxide film-nitride film-upper oxide film (ONO) by forming a lower oxide film on the floating gate by thermally oxidizing the first polycrystalline silicon layer constituting the floating gate, forming a silicon nitride film on the lower oxide film by using a thermal process, and then forming and annealing an upper oxide film on the silicon nitride film by using a thermal process.