IP Library Granted Patent US 7,259,098
Granted Patent B2
US 7,259,098 · App. 10/747,599 · Granted Aug 21, 2007

Methods for fabricating semiconductor devices

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Quick Facts
Patent No.
US 7,259,098
App. No.
10/747,599
Granted
Aug 21, 2007
Kind
B2
Abstract

Semiconductor devices and methods for fabricating a semiconductor devices are disclosed. A disclosed method comprises: forming a first gate electrode functioning as a flash memory; forming first spacers on sidewalls of the first gate electrode; forming a second gate electrode functioning as a normal gate electrode; forming a source/drain region with a shallow junction by performing a first ion implantation process using at least one of the first spacers as a mask; forming second spacers on a sidewall of the first spacer and on sidewalls of the second gate electrode; forming a source/drain region with a deep junction by performing a second ion implantation process using the second spacers as a mask.

Claims (13)

1. A method for fabricating a semiconductor device comprising:

forming a first gate electrode including a dielectric layer, a first conducting layer formed on the dielectric layer, and a first insulating layer formed on the conducting layer on a substrate, the first gate electrode functioning as a flash memory;

forming first spacers on sidewalls of the first gate electrode;

forming a second gate electrode comprising a gate oxide layer and a second conducting layer on the substrate, the second gate electrode functioning as a normal gate electrode;

performing a first ion implantation process using at least one of the first spacers as a mask to form a shallow junction region for a source/drain region;

forming second spacers on a sidewall of the first spacer and on sidewalls of the second gate electrode; and

performing a second ion implantation process using at least one of the second spacers as a mask to form a deep junction region for the source/drain region.

2. A method as defined in claim 1 , wherein forming the first spacers comprises:

forming a second insulating layer on the substrate and the first gate electrode; and

performing an etch back process on the second insulating layer.

3. A method as defined in claim 1 , wherein forming the second spacers comprises:

forming a third insulating layer on the substrate, the first gate electrode, the first spacers, and the second gate electrode; and

performing an etch back process on the third insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2014
From: DONGBU HITEK CO., LTD.
To: DSS TECHNOLOGY MANAGEMENT, INC.
Reel/Frame 033035/0680 →