Granted Patent B2

US 6,977,201 · App. 10/747,619 · Granted Dec 20, 2005

Abstract

Claims (13)

1. A method of fabricating a flash memory device comprising:

forming a tunnel oxide layer on a semiconductor substrate, at least a portion of said tunnel oxide layer being made of one selected from the group consisting of Y 2 O 3 , Al 2 O 3 , HfO 2 , and ZrO 2 with a conduction band energy level lower than that of SiO 2 ;

forming a floating gate on the tunnel oxide layer;

forming an intergate dielectric layer on the floating gate;

forming a control gate on the intergate dielectric layer;

forming a gate electrode by patterning the tunnel oxide layer, the floating gate, the intergate dielectric layer, and the control gate; and

forming a source/drain region by performing an ion implantation into the substrate using the gate electrode as a mask.

2. The method as defined by claim 1 , wherein forming the tunnel oxide layer comprises:

forming a first tunnel oxide layer on the semiconductor substrate; and

forming a second tunnel oxide layer on the first tunnel oxide layer.

3. The method as defined by claim 2 , wherein the first tunnel oxide layer is made of one selected from the group consisting of Y 2 O 3 , Al 2 O 3 , HfO 2 , and ZrO 2 with a conduction band energy level lower than that of SiO 2 .

4. The method as defined by claim 2 , wherein the second tunnel oxide layer is made of one selected from the group consisting of Y 2 O 3 , Al 2 O 3 , and SiO 2 with a conduction band energy level equal or similar to that of SiO 2 .

5. The method as defined by claim 2 , wherein the first tunnel oxide layer is deposited more thickly than the second tunnel oxide layer.

Assignments (8)