IP Library › Granted Patent US 7,186,649
Granted Patent B2
US 7,186,649 · App. 10/747,946 · Granted Mar 6, 2007

Submicron semiconductor device and a fabricating method thereof

Assignee: Dongbu Electronics Co. Ltd.
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Quick Facts
Patent No.
US 7,186,649
App. No.
10/747,946
Granted
Mar 6, 2007
Kind
B2
Abstract

A method of forming a pattern finer than an existing pattern in a semiconductor device using an existing light source and a hard mask, and a method of removing the hard mask which is used as an etching mask. The method includes forming an oxide layer on a substrate; forming a polysilicon layer on the oxide layer; forming a hard mask on the polysilicon layer; depositing photoresist on the hard mask and patterning the hard mask by using the photoresist; and etching the polysilicon layer using the pattern embodied by the hard mask. By fabricating a gate oxide with a finer linewidth using a hard mask and existing equipment, the present invention can control the linewidth required in each product by using an etching process, and, therefore, has advantages such as expandability of process, extension of generality, and maximization of productivity in the production line.

Claims (13)

1. A method of fabricating a submicron semiconductor device comprising:

forming a thermal oxide layer on a substrate;

forming a polysilicon layer on said thermal oxide layer;

forming a hard mask on said polysilicon layer, wherein said hard mask is a SiH 4 oxide deposited by PE-CVD;

depositing a photoresist on said hard mask and patterning said photoresist by using a mask;

etching said hard mask by plasma etching to form a thin hard mask pattern by using the photoresist pattern as an etching mask so that the hard mask pattern can have a narrower width than that of the photoresist pattern;

etching said polysilicon layer by using the hard mask pattern as an etching mask;

etching a polymer formed as a residual product resulting from etching said polysilicon layer; and

selectively removing said hard mask pattern using an etching process while protecting said polysilicon layer and said thermal oxide layer from etching, wherein said etching process is performed by HF gas on a hot plate, said HF is generated gasifying a solution of about 39% HF, as the same time that said gas protects a polysilicon gate and a gate oxide, said HF gas is formed through spraying N 2 gas onto the surface of a chemical bath containing HF solution, and said hot plate has a temperature of about 50˜90° C.

2. The method according to claim 1 , further comprising depositing an ARC on said hard mask so as to lower reflectivity.

3. The method according to claim 1 , wherein an etching rate of said etching process is less than about 1 Å/min for said gate oxide and more than about 200 Å/min for said hard mask.

4. The method according to claim 1 , wherein said photoresist patterning is performed using a KrF Laser as a light source.

5. The method according to claim 1 , wherein said polymer is etched by using a dilute HF cleaning process.

Assignments (3)
CHANGE OF NAME Recorded Jun 7, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017976/0680 →
CHANGE OF NAME Recorded Aug 22, 2005
From: DONGBU ELECTRONICS CO., LTD.
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 016908/0209 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2003
From: SHIM, JOON BUM; HWANG, HAN GYOO; LEE, KANG HYUN
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 014855/0446 →
Priority Claims (2)
KR 10-2003-0022107 · Apr 8, 2003 · national
KR 10-2003-0047491 · Jul 12, 2003 · national
Continuity (1)
Related Publication 20040203236A1 · Oct 14, 2004