Semiconductor device and a method of manufacturing the same and designing the same
View Patent ↗There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP 1 of relatively wider area and the second dummy pattern DP 2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP 1 occupy a relatively wide region among the dummy region FA.
1. A semiconductor device comprising:
semiconductor elements formed in a semiconductor substrate;
a first interlayer insulation film formed over said semiconductor elements; and
first wirings, second wirings and third wirings formed on said first interlayer insulation film, respectively,
wherein said third wirings are electrically connected with said semiconductor elements,
wherein said first and second wirings are not electrically connected with said semiconductor elements,
whereing all of said first, second and third wirings are formed at a same layer,
wherein said second wirings are formed regularly, and
wherein each of said first wirings has a width larger then a width of each second wiring such that a planar size of each first wiring is larger than a planar size of each second wiring.
2. A semiconductor device according to claim 1 , further comprising:
a second interlayer insulation film formed on said first, second and third wirings; and
fourth wirings formed on said second interlayer insulation film and not electrically connected with said semiconductor elements,
wherein said fourth wirings are formed regularly.
3. A semiconductor device according to claim 1 ,
wherein said first wirings and said second wirings are arranged in the row direction and/or column direction, respectively.
4. A semiconductor device according to claim 1 ,
wherein said first wirings and said second wirings are dummy wirings, respectively.
5. A semiconductor device according to claim 1 , further comprising:
a second insulation film formed over said first interlayer insulation film and said first, second and third wirings,
wherein said second insulation film has an outer main surface that is substantially flattened.
6. A semiconductor device according to claim 1 ,
wherein said first, second and third wirings are formed of aluminum or copper, respectively.
7. A semiconductor device comprising:
semiconductor elements formed in a semiconductor substrate;
a first interlayer insulation film formed over said semiconductor elements; and
first wirings, second wirings and third wirings formed on said first interlayer insulation film, respectively,
wherein said third wirings are electrically connected with said semiconductor elements,
wherein said first and second dummy wirings are not electrically connected with said semiconductor elements,
wherein all of said first, second and third wirings are formed at a same layer,
wherein said first wirings are formed regularly,
wherein said second wirings are formed regularly, and
wherein a planar size of each first wiring is larger than a planar size of each second wiring.
8. A semiconductor device according to claim 7 , wherein said first wirings and said second wirings are arranged in the row direction and/or column direction, respectively.
9. A semiconductor device according to claim 7 , further comprising:
a second interlayer insulation film formed on said first, second and third wirings; and
fourth wirings formed on said second interlayer insulation film and not electrically connected with said semiconductor elements,
wherein said fourth wirings are formed regularly.
10. A semiconductor device comprising:
semiconductor elements formed in a semiconductor substrate:
a first interlayer insulation film formed over the semiconductor elements;
first wirings formed on the first interlayer insulation film and electrically connected with the semiconductor elements;
first dummy wirings and second dummy wirings formed on the first interlayer insulation film and not electrically connected with the semiconductor elements;
a second interlayer insulation film formed on the first wirings and on the first and second dummy wirings; and
third dummy wirings formed on the second interlayer insulation film and not electrically connected with said semiconductor elements,
wherein both the first dummy wirings and the second dummy wirings are formed at a same layer as the first wirings,
wherein each of the first dummy wirings has a width larger than a width of each second dummy wiring such that a planar size of each first dummy wiring is larger than a planar size of each second dummy wiring, and
wherein the second dummy wirings and the third dummy wirings are formed regularly.