Method for fabricating a trench transistor of semiconductor device
View Patent ↗A method for fabricating a semiconductor transistor including forming a first insulating layer on a semiconductor substrate; forming an LDD region using ion implantation; patterning the first insulating layer; forming a trench in the substrate; forming a trench gate by depositing and planarizing a second insulating layer and a conductor on the substrate with the trench formed therein; forming a photoresist pattern on the substrate; forming source/drain regions by performing an ion implantation using the photoresist pattern as a mask; and removing the photoresist pattern and the first insulating layer. Thus, a method for fabricating a semiconductor transistor according to the present invention can reduce source/drain resistances and gate resistance by forming a trench type gate and can efficiently control a short channel effect.
1. A method for fabricating a semiconductor transistor, comprising:
forming a first insulating layer on a substrate;
performing an ion implantation for forming a lightly-doped drain (LDD) region in the substrate;
patterning the first insulating layer;
forming a trench in the substrate, the trench extending through the first insulating layer and the LDD region, and the trench extending into a portion of the substrate;
forming a trench gate having sidewalls by depositing and planarizing a second insulating layer and a conductor on the substrate with the trench formed therein, the trench gate comprising the second insulating layer and the conductor, wherein the trench gate is formed after forming the LDD region;
anisotropically etching the first insulating layer, except for a portion of the first insulating layer positioned on sidewalls of the trench gate, to form spacers; and
forming source/drain regions by performing an ion implantation on the substrate using the spacers and the trench gate as a mask, wherein the source/drain regions are formed after forming the LDD region.
2. The method of claim 1 , further comprising performing a thermal process after forming the source/drain regions.
3. The method of claim 1 , wherein the first insulating layer is an oxide layer or a nitride layer.
4. The method of claim 1 , wherein the conductor comprises one selected from the group consisting of polysilicon, tungsten alloys, titanium alloys, and tantalum alloys.
5. The method of claim 1 , wherein the energy of the ion implantation for forming the LDD region is between 10 keV and 80 keV.
6. The method of claim 1 , wherein the energy of the ion implantation for forming the source/drain regions is between 10 keV and 100 keV.
7. The method of claim 1 , wherein the trench is formed by dry etching.
8. The method of claim 1 , wherein the trench is formed by a dry etching using an angle etching and chemical dry etching.
9. The method of claim 8 , wherein lower edges of the trench are formed in a rounded shape.
10. The method of claim 8 , wherein the chemical dry etching uses CF 4 /O 2 or CHF 3 /O 2 .
11. The method of claim 1 , wherein planarizing a second insulating layer and a conductor comprises a CMP process using the first insulating layer as an etch-stop layer.