Digital undersampling
View Patent ↗A method and system for processing a signal are disclosed. The method comprises: applying an algorithm to selectively negate a plurality of samples of the signal to provide negated and non-negated samples of the signal, and use the negated and non-negated samples as in-phase (I) and/or quadrature (Q) components of a plurality of complex samples, the algorithm being such that the plurality of complex samples are equivalent to the result that would be obtained by applying an effective sampling function to the signal, and selecting a beat frequency of the effective sampling function by adjusting the algorithm.
1. A signal processing system, comprising:
an inverter configured to selectively negate a plurality of samples of a signal to provide negated and non-negated samples of the signal; and
a first low pass filter configured to use a first set of selected ones of the negated and non-negated samples as in-phase (I) of a plurality of complex samples and a second low pass filter configured to use a second set of selected ones of the negated and non-negated samples as quadrature (Q) components of the plurality of complex samples;
wherein the plurality of complex samples correspond to the output of an effective sampling function;
and further comprising a processor configured to select a beat frequency of the effective sampling function by adjusting the algorithm, including by iteratively adjusting one or both of: a negation sequence in accordance with which samples comprising the plurality of samples of the signal are negated and a sorting sequence in accordance with which samples are sorted into I and Q components, until a beat frequency resulting in an output having a desired characteristic is achieved.
2. A signal processing system as recited in claim 1 , wherein the effective sampling function is a complex sampling function.
3. A signal processing system as recited in claim 1 , wherein the plurality of samples comprises a plurality of digital samples at a non-zero carrier frequency.
4. A signal processing system as recited in claim 1 , wherein the plurality of complex samples comprises a plurality of complex samples of the signal at baseband.
5. A signal processing system as recited in claim 1 , wherein the signal is a modulated signal.
6. A signal processing system as recited in claim 1 , wherein the signal is a modulated signal and the plurality of complex samples comprise a directly downconverted complex image of the modulated signal.
7. A signal processing system as recited in claim 1 , wherein each of the plurality of samples results in either an I component of one of the plurality of complex samples or a Q component of one of the plurality of complex samples.
8. A signal processing system as recited in claim 1 , wherein each of the plurality of samples results in both an I component of one of the plurality of complex samples and a Q component of one of the plurality of complex samples.
9. A signal processing system as recited in claim 1 wherein selecting the beat frequency of the effective sampling function comprises reversing the order of sorting to select a positive image or a negative image.
10. A signal processing system as recited in claim 1 wherein adjusting the algorithm comprises modifying a beat coefficient.
11. A signal processing system as recited in claim 10 , wherein adjusting the algorithm comprises modifying a beat coefficient “n” comprising an integer by which the rate of complex sampling events “T” is multiplied to yield the period of the beat frequency of the effective sampling function.
12. A signal processing system as recited in claim 10 , wherein the plurality of complex samples includes a baseband signal having a bandwidth, and the effective sampling function includes a beat frequency greater than one half of the bandwidth.
13. A signal processing system as recited in claim 1 , further comprising an analog to digital converter configured to generate the plurality of samples of the signal.
14. A signal processing system as recited in claim 1 , wherein one or more of the inverter, the first low pass filter, and the second low pass filter comprise a field programmable gate array (FPGA).
15. A signal processing system as recited in claim 1 , wherein one or more of the inverter, the first low pass filter, and the second low pass filter, and the processor comprises an integrated circuit.