Semiconductor device including p-channel type transistor, and production method for manufacturing such semiconductor device
View Patent ↗In a semiconductor device including at least one p-channel type MOS transistor, a silicon dioxide layer is formed on a silicon substrate, and a gate electrode is formed on the silicon dioxide layer. The gate electrode silicon has a three-layered structure including a silicon-seed layer formed on the silicon dioxide layer, a silicon/germanium layer formed on the silicon-seed layer, and a polycrystalline silicon layer on the silicon/germanium layer. An average grain size of polycrystalline silicon in the polycrystalline silicon layer is at most 100 nm, and p-type impurities are substantially uniformly distributed in the gate electrode along a height thereof, and the germanium atoms are diffused from the silicon/germanium layer into the silicon-seed layer at high density.
1. A production process for manufacturing a semiconductor device including at least one p-channel type MOS transistor, which process comprises:
preparing a semiconductor device;
forming a gate insulating layer on said semiconductor substrate;
forming a gate electrode on said gate insulating layer, said gate electrode having a multi-layered structure including a silicon-seed layer formed as a lowermost layer on said gate insulating layer, a polycrystalline silicon layer formed as an uppermost layer above said lowermost layer, and a silicon/germanium layer formed as an intermediate layer between said lowermost and uppermost layers, the formation of said uppermost layer being carried out at a higher process temperature than a process temperature at which said lowermost and intermediate layers are formed;
implanting p-type impurities in said gate electrode; and
annealing said semiconductor substrate at a higher process temperature than the process temperature at which said uppermost layer is formed, such that said p-type impurities are substantially uniformly distributed in said gate electrode along a height thereof, and the germanium atoms are diffused from said intermediate layer into said lowermost layer at high density.
2. A production process as set forth in claim 1 , wherein the formation of said lowermost, intermediate, and uppermost layers is carried out by using a chemical vapor deposition method.
3. A production process as set forth in claim 2 , wherein said chemical vapor deposition method is performed by a leaf-type chemical vapor deposition apparatus, the formation of said lowermost and intermediate layers is carried out at a process temperature falling a range between approximately 550° C. and approximately 650° C., and the formation of said uppermost layer is carried out at a process temperature falling in a range between approximately 680° C. and approximately 800° C.
4. A production process as set forth in claim 2 , wherein said chemical vapor deposition method is performed by a batch-type chemical vapor deposition apparatus, the formation of said lowermost an intermediate layers is carried out at a process temperature falling a range between approximately 450° C. and approximately 550° C., and the formation of said uppermost layer is carried out at a process temperature falling in a range between approximately 600° C. and approximately 650° C.
5. A production process as set forth in claim 1 , wherein both a p-type drain-formation region and a p-type source-formation region are defined in said semiconductor substrate while implanting said p-type impurities in said gate electrode, and the respective p-type drain-formation and p-type source-formation regions are produced as a drain region and a source region while annealing said semiconductor substrate at the higher process temperature than the process temperature at which said uppermost layer is formed.
6. A production process as set forth in claim 1 , further comprising forming an insulating side wall around said gate electrode, wherein the formation of said insulating side wall is performed prior to the annealing of said semiconductor substrate.
7. A production process as set forth in claim 1 , further comprising forming an insulating side wall around said gate electrode, wherein the formation of said insulating side wall is performed after the annealing of said semiconductor substrate.