System for measuring signal path resistance for an integrated circuit tester interconnect structure
View Patent ↗Resistances of signal paths within a interconnect structure for linking input/output (I/O) ports of an integrated circuit (IC) tester to test points of an IC are measured by the IC tester itself. To do so the interconnect structure is used to link the tester's I/O ports to a similar arrangement of test points linked to one another through conductors. Drivers within the tester, which normally transmit digital test signals to IC test points via the I/O ports when the IC is under test, are modified so that they may also either transmit a constant current through the I/O ports or link the I/O ports to ground or other reference potential. The tester then transmits known currents though the signal paths interconnecting the tester's I/O ports. Existing comparators within the tester normally used to monitor the state of an IC's digital output signals are employed to measure voltage drops between the I/O ports, thereby to provide data from which resistance of signal paths within the interconnect structure may be computed.
1. A channel for an integrated circuit tester, the channel comprising:
an input/output (I/O) port;
a first transistor for turning on and off in response to a first control signal supplied thereto, said first transistor having a first terminal linked to said I/O port, and having a second terminal, said first transistor conductively linking said first and second terminals through low impedance when turned on and isolating said first and second terminals through high impedance when turned off;
a second transistor for turning on and off in response to a second control signal supplied thereto, having a third terminal linked to said I/O port, and having a fourth terminal, said second transistor conductively linking said third and fourth terminals through low impedance when turned on and isolating said third and fourth terminals through high impedance when turned off;
reference signal generation means for selectively supplying one of a first reference voltage and a constant current to said fourth terminal selected in response to a third control signal supplied thereto;
a source of second reference voltage;
comparator means linked to said I/O port for producing an indicating signal indicating whether a voltage at said I/O port exceeds an adjustable reference voltage supplied thereto; and
control means for supplying said first, second and third control signals and said adjustable reference voltage to said first and second transistors, said reference signal generation means and said comparator respectively.
2. The channel in accordance with claim 1 wherein said reference signal generation means comprises:
a first voltage source;
a current source; and
means for alternatively connecting either one of said first voltage source and said current source to said second terminal in response to said third control signal.
3. The channel in accordance with claim 1 wherein said means for applying said second reference voltage to said fourth terminal comprises:
a node at ground potential;
a source of said second reference voltage, and
switch means for selectively linking either of said source of second reference voltage and node to said fourth terminal in response to said third control signal.