Output driver circuit with automatic slew rate control and slew rate control method using the same
The output signal from an output driver is compared with first and second reference voltages. A first comparison output signal is generated which exhibits a voltage transition when the output signal reaches the first reference voltage, and a second comparison output signal is generated which exhibits a voltage transition when the output signal reaches the second reference voltage. First and second pulse widths values are then compared. The first pulse width value corresponds to a time delay difference between the voltage transition of the first comparison output signal and the voltage transition of the second comparison output signal, and the second pulse width value corresponds to a target slew rate of the output signal from the output driver. The slew rate of the output signal is decrease when the first pulse width value is smaller than the second pulse width value, and the slew rate of the output signal is increased when the first pulse width value is larger than the second pulse width value.
1. A circuit for outputting a signal having a target slew rate, said circuit comprising:
an output driver that outputs an output signal and is responsive to a slew rate control signal to increase or decrease a slew rate of the output signal;
a slew rate detection circuit that compares the output signal from the output driver with a first reference voltage and generates a first comparison output signal which exhibits a voltage transition when the output signal reaches the first reference voltage, and compares the output signal with a second reference voltage and generates a second comparison output signal which exhibits a voltage transition when the output signal reaches the second reference voltage;
a pulse width comparison circuit that compares a first pulse width value with a second pulse width value, the first pulse width value corresponding to a time delay difference between the voltage transition of the first comparison output and the voltage transition of the second comparison output signal, and the second pulse width value corresponding to a target slew rate of the output signal from the output driver; and
a slew rate control circuit that generates the slew rate control signal in response to a signal output from the pulse width comparison circuit.
2. The circuit of claim 1 , wherein the level of the second reference voltage is higher than that of the first reference voltage.
3. The circuit of claim 1 , wherein the slew rate control circuit generates a first slew rate control signal which causes the output driver to decrease the slew rate of the output signal when the signal output from the pulse width comparison circuit indicates that the first pulse width value is smaller than the second pulse width value, and generates a second slew rate control signal which causes the output driver to increase the slew rate of the output signal when the signal output from the pulse width comparison circuit indicates that the first pulse width value is greater than the second pulse width value.
4. The circuit of claim 1 , wherein the output driver is included in a semiconductor memory device, and wherein the target slew rate is set from external the semiconductor memory device.
5. The circuit of claim 1 , wherein the output driver is included in a semiconductor memory device, and wherein target slew rate is set from external the semiconductor device during a mode register set (MRS) operation.
6. A method of controlling the slew rate of an output signal output from an output driver, the method comprising:
comparing the output signal from the output driver with a first reference voltage and generating a first comparison output signal which exhibits a voltage transition when the output signal reaches the first reference voltage;
comparing the output signal with a second reference voltage and generating a second comparison output signal which exhibits a voltage transition when the output signal reaches the second reference voltage;
comparing a first pulse width value with a second pulse width value, the first pulse width value corresponding to a time delay difference between the voltage transition of the first comparison output signal and the voltage transition of the second comparison output signal, and the second pulse width value corresponding to a target slew rate of the output signal from the output driver; and
decreasing the slew rate of the output signal when the first pulse width value is smaller than the second pulse width value, and increasing the slew rate of the output signal when the first pulse width value is larger than the second pulse width value.
7. The method of claim 6 , wherein the level of the second reference voltage is higher than that of the first reference voltage.
8. The method of claim 6 , wherein the output driver is included in a semiconductor memory device, and wherein the target slew rate is set from external the semiconductor memory device.
9. The method of claim 6 , wherein the output driver is included in a semiconductor memory device, and wherein target slew rate is set from external the semiconductor device during a mode register set (MRS) operation.