Phase-change memory element and method of storing data therein

1. A method of operating a phase-change memory element, said memory element including a phase-change material, said method comprising:

providing said phase-change memory element including said phase-change material; and

programming said phase-change memory element from a first memory state having a first threshold voltage to a second memory state having a second threshold voltage, wherein said phase-change material is in a saturated condition in said first memory state and said second memory state.

2. The method of claim 1 , wherein said phase-change material is in an amorphous phase in said first memory state and said second memory state.

3. The method of claim 1 , wherein said phase-change material includes a chalcogen element.

4. A method of operating a phase-change memory element, said memory element comprising a phase-change material, said method comprising:

providing said phase-change memory element including said phase-change material; and

programming said phase-change memory element from a first memory state to a second memory state, said phase-change material being in an amorphous phase in said first memory state and said second memory state.

5. The method of claim 4 wherein said phase-change material includes a chalcogen element.

6. A method of reading the current memory state of a phase-change memory element including a phase-change material, said phase-change memory element having at least a first memory state with a first threshold voltage and a second memory state with a second threshold voltage, said method comprising:

providing said phase-change memory element including said phase-change material; and

applying a discriminating voltage across said memory element, said discriminating voltage being between said first threshold voltage and said second threshold voltage.

7. The method of claim 6 , wherein said phase-change material includes a chalcogen element.

8. An electrically programmable memory element having a plurality of memory states, comprising:

a phase-change material, said phase-change material being in an amorphous phase in each of said memory states.

9. The memory element of claim 8 , wherein each of said memory states has a corresponding threshold voltage.

10. The memory element of claim 8 , wherein said phase-change material includes a chalcogen element.

11. An electrically programmable memory array, comprising:

a row line;

a column line; and

a memory element coupled to said row line and said column line, said memory element having at least a first memory state and a second memory state, said memory element including a phase-change material, said phase-change material being in an amorphous phase in said first memory state and in said second memory state.

12. The memory array of claim 11 , wherein said memory element is coupled to said row line or said column line through an isolation device.

13. The memory array of claim 11 , wherein said isolation device is selected from the group consisting of diode and transistor.

14. The memory array of claim 11 , wherein each of said first memory state has a first threshold voltage and said second memory state has a second threshold voltage.

15. The memory element of claim 11 , wherein said phase-change material includes a chalcogen element.

16. An electrically programmable memory element having at least a first memory state and a second memory state, comprising:

a phase-change material wherein said first memory state has a first threshold voltage and said second memory state has a second threshold voltage, wherein said phase-change material is in a saturated condition is said first memory state and said second memory state.

17. The memory element of claim 16 , wherein said phase-change material includes a chalcogen element.

18. An electrically programmable memory array, comprising:

a row line;

a column line; and

a memory element including a phase-change material, said memory element coupled to said row line and said column line, said memory element having at least a first memory state with a first threshold voltage and a second memory state with a second threshold voltage, wherein said phase-change material is in a saturated condition is said first memory state and said second memory state.

19. The memory array of claim 18 , wherein said memory element is coupled to said row line or said column line through an isolation device.

20. The memory array of claim 19 , wherein said isolation device is selected from the group consisting of diode and transistor.

21. The memory element of claim 18 , wherein said phase-change material includes a chalcogen element.