Semiconductor device and method for fabricating the same
View Patent ↗Impurities for threshold voltage adjustment are implanted using a resist film and a protective dielectric as implantation masks from directions inclined at 10° through 30° with respect to the direction vertical to the principal surface of a semiconductor substrate 1 when viewed in cross section taken along the gate width direction. Thus, first low-concentration impurity implantation regions are formed to overlap each other in the central part of an active region for a memory cell MIS transistor Mtrs of an SRAM. Furthermore, after an isolation is formed, a second low-concentration impurity implantation region is formed in an active region for each of MIS transistors Ltr, Mtrs and Mtrl by implanting impurity ions without using implantation masks. The MIS transistors Ltr, Mtrs and Mtrl formed after the completion of the fabricating process have substantially the same threshold voltage.
1. A semiconductor device comprising:
a semiconductor substrate including a first active region and a second active region;
a first MIS transistor provided in the first active region and including a first gate electrode having a first gate width; and
a second MIS transistor provided in the second active region and including a second gate electrode having a second gate width wider than the first gate width;
wherein the first MIS transistor includes, in the first active region below the first gate electrode, a first threshold-voltage-adjusting impurity diffusion region including two first impurity diffusion regions, which extend from both end parts of the first active region that are located in the gate width direction of the first gate electrode, and come into contact with each other in the central part of the first active region; and
the second MIS transistor includes, in the second active region below the second gate electrode, a second threshold-voltage-adjusting impurity diffusion region including two second impurity diffusion regions, which extend from both end parts of the second active region that are located in the gate width direction of the second gate electrode, and located apart from each other with the central part of the second active region interposed therebetween.
2. The semiconductor device of claim 1 , wherein
the first threshold-voltage-adjusting impurity diffusion region of the first MIS transistor further includes, in the first active region below the first gate electrode, a third impurity diffusion region having a substantially uniform impurity concentration in the gate width direction of the first gate electrode.
3. The semiconductor device of claim 1 , wherein
the second threshold-voltage-adjusting impurity diffusion region of the second MIS transistor further includes, in the second active region below the second gate electrode, a third impurity diffusion region having a substantially uniform impurity concentration in the gate width direction of the second gate electrode.
4. The semiconductor device of claim 2 , wherein
the second threshold-voltage-adjusting impurity diffusion region of the second MIS transistor further includes, in the second active region below the second gate electrode, a fourth impurity diffusion region having a substantially uniform impurity concentration in the gate width direction of the second gate electrode.
5. The semiconductor device of claim 1 , wherein:
the semiconductor substrate includes a third active region;
a third MIS transistor having a third gate electrode having a third gate width wider than the first gate width is provided in the third active region; and
the third MIS transistor includes, in the third active region below the third gate electrode, a third threshold-voltage-adjusting impurity diffusion region including a third impurity diffusion region having a substantially uniform impurity concentration in the gate width direction of the third gate electrode.
6. The semiconductor device of claim 5 , wherein:
the semiconductor device comprises an SRAM including a memory cell region and a peripheral circuit, and a logic circuit;
the first MIS transistor is a memory cell transistor arranged in the memory cell region of the SRAM;
the second MIS transistor is a peripheral transistor arranged in the peripheral circuit of the SRAM; and
the third MIS transistor is a logic MIS transistor arranged in the logic circuit.