Method for testing signal paths between an integrated circuit wafer and a wafer tester
View Patent ↗Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test signals between pairs of its ports through those signal paths and the interconnecting conductors within the reference wafer. A parametric test unit within the tester can also determine impedances of the signal paths through the interconnect structure by comparing magnitudes of voltage drops across pairs of its I/O ports to magnitudes of currents it transmits between the I/O port pairs.
1. A method of testing an interconnect structure, comprising:
providing a semiconductor device tester having a plurality of ports;
providing an interconnect structure to interconnect ones of the plurality of ports with corresponding ones of a plurality of probes, wherein the plurality of probes are in an arrangement substantially similar to an arrangement of die pads on a semiconductor wafer of semiconductor devices;
associating a first one of the probes, the first one of the probes having a corresponding first port on the semiconductor tester, with a second one of the probes, the second one of the probes having a corresponding second port on the semiconductor tester, thereby establishing an expected signal path from the first port to the second port; and
transmitting a test signal on the first port; and
determining whether an expected signal appears at the second port.
2. The method in accordance with claim 1 wherein the associating comprises providing a test wafer having a plurality of contact pads in an arrangement substantially similar to the arrangement of die pads and a conductor making an electrical connection between a first contact pad in a first location on the wafer corresponding to the first probe and a second contact pad in a second location on the wafer corresponding to the second probe.
3. The method in accordance with claim 1 further comprising measuring a voltage at the second port.
4. The method in accordance with claim 3 further comprising computing a ratio of said voltage to a current of said test signal.
5. A method of producing a tested interconnect structure, comprising:
providing an integrated circuit (IC) tester having a plurality of ports;
providing an interconnect structure to interconnect ones of the plurality of ports with corresponding ones of a plurality of probes, wherein the plurality of probes are in an arrangement substantially similar to an arrangement of die pads on a semiconductor wafer of semiconductor devices;
providing a reference wafer having a plurality of test pads in an arrangement substantially similar to the arrangement of die pads, a reference point, and at least one conductor interconnecting said test pads with said reference point, the test pads and the reference point adapted to contact respective ones of the probes; and
transmitting a test signal on one of the ports expectedly connected to a one of said test pads via a first probe tip; and
measuring an expected signal on a port expectedly connected to the reference port via a second probe tip.
6. The method in accordance with claim 5 further comprising:
grounding another of said ports expectedly connected to another of said test pads; measuring a magnitude of said test signal; and
calculating a path resistance in accordance with the measured magnitude of said test signal.
7. The method in accordance with claim 5 further comprising:
open circuiting another of said ports expectedly connected to another of said test pads;
measuring a magnitude of said test signal; and
calculating a path resistance in accordance with the measured magnitude of said test signal.
8. The method in accordance with claim 5 further comprising:
measuring a magnitude of said test signal; and
calculating a path resistance in accordance with the measured magnitude of said test signal.
9. A method of producing a tested probe card assembly comprising,
providing an integrated circuit (IC) tester having test ports:
providing semiconductor devices having first test points on a wafer to be tested;
providing a reference wafer having a plurality of second test points in an arrangement matching an arrangement of the first test points, and a conductor interconnecting at least two of the second test points;
providing a probe card assembly to interconnect at least a portion of the second test points with at least a portion of the test ports;
transmitting a test signal from one of the test ports of the IC tester to another of said test ports via a signal path within said probe card assembly and said conductor; and
determining whether the test signal arrives at said another of the test ports.