Electronic components such as thin array plastic packages and process for fabricating same
View Patent ↗A process for fabricating an integrated circuit package includes establishing a plating mask on a first surface of a metal carrier. The plating mask defines a plurality of components including a die attach pad, at least one row of contact pads and at least one additional electronic component. A plurality of metallic layers are deposited on exposed portions of the first surface of the metal carrier. The plating mask is stripped from the metal carrier, leaving the plurality of metallic layers in the form of the plurality of components. A semiconductor die is mounted to die attach pad and pads of the semiconductor die are electrically connected to ones of the contact pads and to the additional electronic component. The first surface of the metal carrier is overmolded to encapsulate the plurality of components and the semiconductor die and the metal carrier is etched away.
1. A process for fabricating an integrated circuit package, comprising:
establishing a plating mask on a first surface of a metal carrier, the plating mask defining a plurality of components including at least one die attach pad, at least one row of contact pads and at least one additional electronic component;
depositing a plurality of metallic layers on exposed portions of said first surface of said metal carrier, thereby forming said plurality of components;
stripping said plating mask from said metal carrier and leaving said plurality of metallic layers in the form of said plurality of components;
mounting at least one semiconductor die to a respective one of said at least one die attach pad such that each die attach pad has a respective semiconductor die mounted thereon and pads of each said respective semiconductor die are electrically connected to ones of said contact pads and to said at least one additional electronic component;
overmolding said first surface of said metal carrier to encapsulate said plurality of components and said at least one semiconductor die; and
etching away said metal carrier.
2. The process according to claim 1 , wherein etching away said metal carrier includes etching a first one of said metallic layers, thereby providing indentations at each of said plurality of components.
3. The process according to claim 2 , further comprising solder mask printing to cover passive ones of said components and leaving exposed portions of said components in ones of said indentations.
4. The process according to claim 1 , wherein said solder mask printing forms a pattern for solder ball attachment to said at least one die attach pad and said contact pads and said process further comprises fixing a plurality of solder balls at said exposed portions of said components.
5. The process according to claim 1 , wherein said at least one additional electronic component is selected from the group consisting of at least one capacitor, at least one inductor and both a capacitor and an inductor.
6. The process according to claim 1 , wherein said establishing a plating mask comprises establishing a plating mask on a first surface of a metal carrier, the plating mask defining a plurality of components including two die attach pads, at least one row of contact pads, an inductor and a capacitor.
7. The process according to claim 6 , wherein said inductor and said capacitor are disposed between said die attach pads.
8. The process according to claim 1 , wherein said mounting at least one semiconductor die comprises:
mounting each said at least one semiconductor die to said respective one of said at least one die attach pad; and
wire bonding each said at least one semiconductor die to ones of said contact pads and to said additional electronic component.
9. The process according to claim 1 , wherein in said establishing a plating mask on said first surface of a metal carrier, said plurality of components further includes a circuit pattern of traces extending from said at least one row of contact pads to ends proximal said die attach pad.
10. The process according to claim 9 , wherein in said establishing a plating mask on said first surface of a metal carrier, said additional electronic component comprises at least one capacitor and said circuit pattern further includes a respective trace extending in from each said at least one capacitor, to an end proximal said die attach pad.
11. The process according to claim 10 , wherein said mounting at least one semiconductor die comprises:
mounting each said at least one semiconductor die to said respective one of said at least one die attach pad; and
wire bonding each said semiconductor die to ones of the traces.
12. The process according to claim 10 , wherein said mounting at least one semiconductor die comprises:
mounting each said at least one semiconductor die in a flip chip orientation to said respective one of said at least one die attach pad such that pads of said semiconductor die are electrically connected to ones of said traces.
13. The process according to claim 1 , further comprising singulating to isolate said integrated circuit package from other packages.
14. The process according to claim 1 , wherein depositing a plurality of metallic layers on exposed portions of said first surface of said metal carrier, includes further masking between depositing of said metallic layers to thereby selectively plate.
15. The process according to claim 1 , wherein said establishing a plating mask comprises:
depositing a photo-imageable mask on the first surface of the metal carrier;
imaging said mask to provide imaged portions that define the desired electronic component; and
developing said mask to remove the imaged portions of the mask.