Efficient use of wafer area with device under the pad approach
More efficient use of silicon area is achieved by incorporating an active device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is below the first metal layer. The active device resides in the substrate below the second metal layer. A layer of dielectric separates the first and second metal layers. A via within the dielectric layer electrically couples the first and second metal layers. A via connects to the active component. Subsequent metal layers can be arranged between the first and second metal layers.
1 . A semiconductor structure comprising:
a pad area; and
an active device of said semiconductor structure disposed below said pad area.
2 . The semiconductor structure as recited in claim 1 wherein said active component comprises a transistor.
3 . The semiconductor structure as recited in claim 1 wherein a component of said semiconductor structure performs a logic function.
4 . The semiconductor structure as recited in claim 1 wherein a component of said semiconductor structure performs a memory function.
5 . The semiconductor structure as recited in claim 1 wherein said active device comprises a first device, said semiconductor structure further comprising:
a non-pad area bounded at least in part by said pad area; and
a second device disposed within said non-pad area.
6 . The semiconductor structure as recited in claim 5 wherein said first and said second devices perform a similar function.
7 . The semiconductor structure as recited in claim 1 wherein said pad area comprises:
a substrate;
a first layer of metal disposed above said substrate wherein said active device is disposed below said first layer of metal;
a second layer of metal disposed above said first layer of metal.
8 . The semiconductor structure as recited in claim 7 further comprising:
a layer of dielectric disposed between said first metal layer and said second metal layer; and
a via disposed within said dielectric layer wherein said via electrically couples said first and said second metal layer.
9 . The semiconductor structure as recited in claim 7 further comprising a subsequent layer of metal between said first and said second metal layers.
10 . A pad area apparatus for a semiconductor structure comprising:
a substrate;
a first layer of metal disposed above said substrate;
a second layer of metal disposed above said first layer of metal; and
an active component wherein said active component is disposed within said substrate.
11 . The pad area apparatus as recited in claim 10 further comprising:
a layer of dielectric disposed between said first metal layer and said second metal layer; and
a via disposed within said dielectric layer wherein said via electrically couples said first and said second metal layer.
12 . The pad area apparatus as recited in claim 10 further comprising a subsequent layer of metal between said first and said second metal layers.
13 - 21 . (canceled)