Multi-stage EPI process for forming semiconductor devices, and resulting device
View Patent ↗The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting substrate, forming a second layer of epitaxial silicon above the first layer of epitaxial silicon, forming a third layer of epitaxial silicon above the second layer of epitaxial silicon, forming a trench isolation region that extends through at least the third layer of epitaxial silicon and forming a portion of a semiconductor device above the third layer of epitaxial silicon within an area defined by the isolation region. In one illustrative embodiment, the device comprises a substrate, a first layer of epitaxial silicon formed above the substrate, a second layer of epitaxial silicon formed above the first layer of epitaxial silicon, a third layer of epitaxial silicon formed above the second layer of epitaxial silicon, a trench isolation region that extends through at least the third layer of epitaxial silicon, the trench isolation region defining an active area, and at least one component of a semiconductor device formed in or above the third layer of epitaxial silicon within the active area.
1. A method, comprising:
forming a first layer of epitaxial silicon having a thickness of approximately 15–30 microns above a surface of a semiconducting substrate;
forming a second layer of epitaxial silicon having a thickness of approximately 0.5–2.0 microns on said first layer of epitaxial silicon;
forming a third layer of epitaxial silicon having a thickness of approximately 20–25 microns on said second layer of epitaxial silicon, wherein said semiconducting substrate is doped with a dopant material of a first type and said second and third layers of epitaxial silicon are doped with a dopant material that is of a type opposite to that of said first type of dopant material, and wherein said first, second and third layers of epitaxial silicon are formed by performing an in situ epitaxial growth process in a single epitaxial reactor;
forming a trench isolation region that extends through at least said third layer of epitaxial silicon; and
forming a portion of a semiconductor device above said third layer of epitaxial silicon within an area defined by said isolation region.
2. The method of claim 1 , wherein said semiconducting substrate is doped with a P-type dopant material and said second and third layers of epitaxial silicon are doped with an N-type dopant material.
3. The method of claim 1 , wherein said semiconducting substrate is doped with an N-type dopant material and said second and third layers of epitaxial silicon are doped with a P-type dopant material.
4. The method of claim 1 , wherein said first layer of epitaxial silicon is an undoped layer of epitaxial silicon.
5. The method of claim 1 , wherein said first layer of epitaxial silicon is doped with either a P-type or an N-type dopant material.
6. The method of claim 1 , wherein said second and third layers of epitaxial silicon are doped layers of epitaxial silicon and wherein said second layer of epitaxial silicon has a greater concentration level of dopant material than said third layer of epitaxial silicon.
7. The method of claim 1 , wherein said substrate has a dopant concentration of approximately 1e 17 –5e 17 ions/cm 3 of a P-type dopant material.
8. The method of claim 7 , wherein said first layer of epitaxial silicon has a dopant concentration less than approximately 1e 15 ions/cm 3 of an N-type dopant material.
9. The method of claim 7 , wherein said second layer of epitaxial silicon has a dopant concentration greater than approximately 5e 17 ions/cm 3 of an N-type dopant material.
10. The method of claim 7 , wherein said third layer of epitaxial silicon has a dopant concentration of approximately 5e 14 –1e 15 ions/cm 3 of an N-type dopant material.
11. The method of claim 1 , wherein said substrate has a dopant concentration of approximately 1e 17 –5e 17 ions/cm 3 of an N-type dopant material.
12. The method of claim 11 , wherein said first layer of epitaxial silicon has a dopant concentration less than approximately 1e 15 ions/cm 3 of a P-type dopant material.
13. The method of claim 11 , wherein said second layer of epitaxial silicon has a dopant concentration greater than approximately 5e 17 ions/cm 3 of a P-type dopant material.
14. The method of claim 11 , wherein said third layer of epitaxial silicon has a dopant concentration of approximately 5e 14 –1e 15 ions/cm 3 of a P-type dopant material.
15. The method of claim 1 , wherein forming a trench isolation region comprises:
performing at least one etching process to form a trench that extends through at least said third layer of epitaxial silicon; and
forming at least one insulating material in said trench.
16. The method of claim 1 , wherein said semiconductor device comprises at least one of a bipolar transistor, a resistor, a diode, a logic device and a memory device.
17. A method, comprising:
forming a first layer of epitaxial silicon having a thickness of approximately 15–30 microns above a surface of a semiconducting substrate, said semiconducting substrate being doped with a first type of dopant material;
forming a second layer of epitaxial silicon having a thickness of approximately 0.5–2.0 microns on said first layer of epitaxial silicon, said second layer of epitaxial silicon being doped with a dopant material that is of a type opposite to that of said first type of dopant material;
forming a third layer of epitaxial silicon having a thickness of approximately 20–25 microns on said second layer of epitaxial silicon, said third layer of epitaxial silicon being doped with a dopant material that is of a type opposite to that of said first type of dopant material, wherein said second layer of epitaxial silicon has a greater concentration level of dopant material than said third layer of epitaxial silicon, wherein said first, second and third layers of epitaxial silicon are formed by perfonning an in situ epitaxial growth process in a single epitaxial reactor;
forming a trench isolation region that extends through at least said third layer of epitaxial silicon; and
forming a semiconductor device above said third layer of epitaxial silicon within an area defined by said isolation region.
18. The method of claim 17 , wherein said semiconducting substrate is doped with a P-type dopant material and said second and third layers of epitaxial silicon are doped with an N-type dopant material.
19. The method of claim 17 , wherein said semiconducting substrate is doped with an N-type dopant material and said second and third layers of epitaxial silicon are doped with a P-type dopant material.
20. The method of claim 17 , wherein said first layer of epitaxial silicon is an undoped layer of epitaxial silicon.
21. The method of claim 17 , wherein said first layer of epitaxial silicon is doped with either a P-type or an N-type dopant material.
22. The method of claim 17 , wherein said substrate has a dopant concentration of approximately 1e 17 –5e 17 ions/cm 3 of a P-type dopant material.
23. The method of claim 22 , wherein said first layer of epitaxial silicon has a dopant concentration less than approximately 1e 15 ions/cm 3 of an N-type dopant material.
24. The method of claim 22 , wherein said second layer of epitaxial silicon has a dopant concentration greater than approximately 5e 17 ions/cm 3 of an N-type dopant material.
25. The method of claim 22 , wherein said third layer of epitaxial silicon has a dopant concentration of approximately 5e 14 –1e 15 ions/cm 3 of an N-type dopant material.
26. The method of claim 17 , wherein said substrate has a dopant concentration of approximately 1e 17 –5e 17 ions/cm 3 of an N-type dopant material.
27. The method of claim 26 , wherein said first layer of epitaxial silicon has a dopant concentration less than approximately 1e 15 ions/cm 3 of a P-type dopant material.
28. The method of claim 26 , wherein said second layer of epitaxial silicon has a dopant concentration greater than approximately 5e 17 ions/cm 3 of a P-type dopant material.
29. The method of claim 26 , wherein said third layer of epitaxial silicon has a dopant concentration of approximately 5e 14 –1e 15 ions/cm 3 of a P-type dopant material.
30. The method of claim 17 , wherein forming a trench isolation region comprises:
performing at least one etching process to form a trench that extends through at least said third layer of epitaxial silicon; and
forming at least one insulating material in said trench.
31. The method of claim 17 , wherein said semiconductor device comprises at least one of a bipolar transistor, a resistor, a diode, a logic device and a memory device.
32. A method, comprising:
performing an in situ epitaxial growth process in a single epitaxial reactor to form:
a first layer of epitaxial silicon having a thickness of approximately 15–30 microns above a surface of a semiconducting substrate, said
semiconducting substrate being doped with a first type of dopant material,
a second layer of epitaxial silicon having a thickness of approximately 0.5–2.0 microns on said first layer of epitaxial silicon, said second layer of epitaxial silicon being doped with a dopant material that is of a type opposite to that of said first type of dopant material, and
a third layer of epitaxial silicon having a thickness of approximately 20–25 microns on said second layer of epitaxial silicon, said third layer of epitaxial silicon being doped with a dopant material that is of a type opposite to that of said first type of dopant material, wherein said second layer of epitaxial silicon has a greater concentration level of dopant material than said third layer of epitaxial silicon;
forming a trench isolation region that extends through at least said second and third layers of epitaxial silicon by performing at least one etching process to form a trench that extends through at least said second and third layers of epitaxial silicon and forming at least one insulating material in said trench; and
forming a semiconductor device above said third layer of epitaxial silicon within an area defined by said isolation region.
33. The method of claim 32 , wherein said semiconducting substrate is doped with a P-type dopant material and said second and third layers of epitaxial silicon are doped with an N-type dopant material.
34. The method of claim 32 , wherein said semiconducting substrate is doped with an N-type dopant material and said second and third layers of epitaxial silicon are doped with a P-type dopant material.
35. The method of claim 32 , wherein said first layer of epitaxial silicon is an undoped layer of epitaxial silicon.
36. The method of claim 32 , wherein said first layer of epitaxial silicon is doped with either a P-type or an N-type dopant material.
37. The method of claim 32 , wherein said semiconductor device comprises at least one of a bipolar transistor, a resistor, a diode, a logic device and a memory device.
38. The method of claim 32 , wherein said substrate has a dopant concentration of approximately 1e 17 –5e 17 ions/cm 3 of a P-type dopant material.
39. The method of claim 38 , wherein said first layer of epitaxial silicon has a dopant concentration less than approximately 1e 15 ions/cm 3 of an N-type dopant material.
40. The method of claim 38 , wherein said second layer of epitaxial silicon has a dopant concentration greater than approximately 5e 17 ions/cm 3 of an N-type dopant material.
41. The method of claim 38 , wherein said third layer of epitaxial silicon has a dopant concentration of approximately 5e 14 –1e 15 ions/cm 3 of an N-type dopant material.
42. The method of claim 32 , wherein said substrate has a dopant concentration of approximately 1e 17 –5e 17 ions/cm 3 of an N-type dopant material.
43. The method of claim 42 , wherein said first layer of epitaxial silicon has a dopant concentration less than approximately 1e 15 ions/cm 3 of a P-type dopant material.
44. The method of claim 42 , wherein said second layer of epitaxial silicon has a dopant concentration greater than approximately 5e 17 ions/cm 3 of a P-type dopant material.
45. The method of claim 42 , wherein said third layer of epitaxial silicon has a dopant concentration of approximately 5e 14 –1e 15 ions/cm 3 of a P-type dopant material.