IP Library › Assignment 037558/0711
Patent Assignment
Reel/Frame 037558/0711

RELEASE OF SECURITY INTEREST

Recorded: 2016-01-19 Received: 2016-01-19 Pages: 101
Assignor
BANK OF AMERICA, N.A.
Executed: 2016-01-15
Assignees
MICROSEMI CORPORATION
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
MICROSEMI SOC CORP., A CALIFORNIA CORPORATION
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
Covered Applications (100)
CONTINUOUSLY INTERLEAVED ERROR CORRECTION
App. No. 14/526,148
→
NETWORK DISTRIBUTED PACKET-BASED SYNCHRONIZATION
App. No. 14/503,082
→
PTP TRANSPARENT CLOCK SYSTEM UPGRADE SOLUTION
App. No. 14/502,877
→
PACKET PROTOCOL PROCESSING WITH PRECISION TIMING PROTOCOL SUPPORT
App. No. 14/494,438
→
MULTI-CHANNEL LOW POWER WAKE-UP SYSTEM
App. No. 14/482,595
→
RADIO WAKE-UP SYSTEM WITH MULTI-MODE OPERATION
App. No. 14/482,527
→
VOLTAGE REGULATOR WITH SWITCHING AND LOW DROPOUT MODES
App. No. 14/454,134
→
INTEGRATED LIMITER AND ACTIVE FILTER
App. No. 14/337,256
→
PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE
App. No. 14/337,865
→
METHOD FOR EFFICIENT FPGA PACKING
App. No. 14/327,842
→
METHOD FOR SECURELY BOOTING TARGET PROCESSOR IN TARGET SYSTEM USING A SECURE ROOT OF TRUST TO VERIFY A RETURNED MESSAGE AUTHENTICATION CODE RECREATED BY THE TARGET PROCESSOR
App. No. 14/322,953
→
DIGITAL PHASE LOCKED LOOP WITH REDUCED CONVERGENCE TIME
App. No. 14/311,638
→
Back to Back Resistive Random Access Memory Cells
App. No. 14/274,417
→
PHASE LOCKED LOOP WITH SIMULTANEOUS LOCKING TO LOW AND HIGH FREQUENCY CLOCKS
App. No. 14/263,286
→
PHASE LOCKED LOOP WITH PRECISE PHASE AND FREQUENCY SLOPE LIMITER
App. No. 14/263,170
→
VOIDLESSLY ENCAPSULATED SEMICONDUCTOR DIE PACKAGE
App. No. 14/258,775
→
CHIP-SCALE ATOMIC GYROSCOPE
App. No. 14/250,059
→
DISTRIBUTED TWO-STEP CLOCK
App. No. 14/210,913
→
System on a Chip FPGA Spatial Debugging Using Single Snapshot
App. No. 14/212,508
→
Background Auto-refresh Apparatus and Method for Non-Volatile Memory Array
App. No. 14/208,513
→
TID HARDENED AND SINGLE EVENT TRANSIENT SINGLE EVENT LATCHUP RESISTANT MOS TRANSISTORS AND FABRICATION PROCESS
App. No. 14/196,667
→
NON-VOLATILE PUSH-PULL NON-VOLATILE MEMORY CELL HAVING REDUCED OPERATION DISTURB AND PROCESS FOR MANUFACTURING SAME
App. No. 14/193,772
→
DISTRIBUTION OF LOCATION INFORMATION
App. No. 14/188,398
→
HYSTERETIC CURRENT MODE CONTROL CONVERTER WITH LOW, MEDIUM AND HIGH CURRENT THRESHOLDS
App. No. 14/171,843
→
MULTIPLEXED SIGMA DELTA MODULATOR
App. No. 14/171,809
→
PACKET-BASED TIMING MEASUREMENT
App. No. 14/171,698
→
TIMING SYNCHRONIZATION FOR NETWORKS WITH RADIO LINKS
App. No. 14/160,449
→
NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY
App. No. 14/155,752
→
UNIVERSAL ASYMMETRY COMPENSATION FOR PACKET TIMING PROTOCOLS
App. No. 14/149,370
→
WIDE RANGE INPUT CURRENT CIRCUITRY FOR AN ANALOG TO DIGITAL CONVERTER
App. No. 14/143,031
→
ON-CHIP PORT CURRENT CONTROL ARRANGEMENT
App. No. 14/143,025
→
PARALLEL CRC COMPUTATION WITH DATA ENABLES
App. No. 14/135,437
→
METHOD OF MAINTAINING AN OUTPUT VOLTAGE OF A POWER CONVERTER
App. No. 14/094,816
→
INTEGRATED START-UP BIAS BOOST FOR DYNAMIC ERROR VECTOR MAGNITUDE ENHANCEMENT
App. No. 14/090,401
→
INTEGRATED CIRCUIT PACKAGE
App. No. 14/084,720
→
LOW LOSS SIC MOSFET
App. No. 14/079,541
→
HIGH ACCURACY 1588 TIMESTAMPING OVER HIGH SPEED MULTI LANE DISTRIBUTION PHYSICAL CODE SUBLAYERS
App. No. 14/041,626
→
DELAY MEASUREMENT IN A POINT TO MULTIPOINT SYSTEM
App. No. 14/040,320
→
AUTO-REFRESH METHOD FOR SONOS NON-VOLATILE MEMORY ARRAY
App. No. 14/013,339
→
SECURE DIGEST FOR PLD CONFIGURATION DATA
App. No. 13/964,692
→
APPARATUS AND METHOD FOR SENSING INCIDENT LIGHT HAVING DUAL PHOTODIODE TO ABSORB LIGHT IN RESPECTIVE DEPLETION REGIONS CONTROLLED BY DIFFERENT BIAS VOLTAGES (AS AMENDED)
App. No. 13/943,305
→
ON-CHIP PROBE CIRCUIT FOR DETECTING FAULTS IN AN FPGA
App. No. 13/933,332
→
ON-CHIP PROBE CIRCUIT FOR DETECTING FAULTS IN AN FPGA
App. No. 13/933,353
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POWER CONVERTER
App. No. 13/921,058
→
MONOLITHICALLY INTEGRATED SIC MOSFET AND SCHOTTKY BARRIER DIODE
App. No. 13/902,382
→
FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES
App. No. 13/898,827
→
INTEGRATED START-UP BIAS BOOST FOR DYNAMIC ERROR VECTOR MAGNITUDE ENHANCEMENT
App. No. 13/897,192
→
TID HARDENED MOS TRANSISTORS AND FABRICATION PROCESS
App. No. 13/895,554
→
METHOD OF ADJUSTING A LOCAL CLOCK IN ASYNCHRONOUS PACKET NETWORKS
App. No. 13/894,638
→
INTEGRATED START-UP BIAS BOOST FOR DYNAMIC ERROR VECTOR MAGNITUDE ENHANCEMENT
App. No. 13/895,236
→
INTEGRATED TECHNIQUE FOR ENHANCED POWER AMPLIFIER FORWARD POWER DETECTION
App. No. 13/894,221
→
POWER OVER ETHERNET FOR BI-DIRECTIONAL ETHERNET OVER SINGLE PAIR
App. No. 13/889,391
→
COMPACT TID HARDENING NMOS DEVICE AND FABRICATION PROCESS
App. No. 13/870,860
→
SQUARE LAW EXTENSION TECHNIQUE FOR HIGH SPEED RADIO DETECTION
App. No. 13/860,875
→
FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS
App. No. 13/840,815
→
Asymmetry Correction for Precise Clock Synchronization Over Optical Fiber
App. No. 13/800,446
→
PHASE LOCKED LOOP FREQUENCY SYNTHESIZER WITH REDUCED JITTER
App. No. 13/778,275
→
DETECTION FOR FOUR PAIR POWERED DEVICES
App. No. 13/769,968
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INFINITE IMPULSE RESPONSE FILTER ARCHITECTURE WITH IDLE-TONE REDUCTION
App. No. 13/746,573
→
POWER DEVICE INTERFACE ARRANGED TO DETECT AMOUNT OF POWER AVAILABLE
App. No. 13/742,377
→
PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE
App. No. 13/742,253
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PULSE TRANSFORMER DRIVER
App. No. 13/718,131
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HIGH EFFICIENCY LED DRIVING METHOD FOR ODD NUMBER OF LED STRINGS
App. No. 13/717,755
→
PACKET-BASED TIMING MEASUREMENT
App. No. 13/679,672
→
PHYSICAL LAYER PROCESSING OF TIMESTAMPS AND MAC SECURITY
App. No. 13/671,480
→
WAN TRANSPORT OF FRAMES WITH MAC SECURITY
App. No. 13/671,516
→
APPARATUS AND METHOD FOR ASSESSING VOLUMETRIC MOISTURE CONTENT AND CONTROLLING AN IRRIGATOR
App. No. 13/665,871
→
CONVERTER WITH HYSTERETIC CONTROL
App. No. 13/659,046
→
POWER SOURCING EQUIPMENT FOR POWER OVER ETHERNET WITH LOW ENERGY STANDBY MODE
App. No. 13/652,504
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METHOD AND APPARATUS FOR LED STRING SHORT CIRCUIT DETECTION AND PROTECTION
App. No. 13/652,495
→
LESS EXPENSIVE HIGH POWER PLASTIC SURFACE MOUNT PACKAGE
App. No. 13/624,775
→
CONTINUOUSLY INTERLEAVED ERROR CORRECTION
App. No. 13/618,380
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FREQUENCY AND PHASE ACQUISITION OF A CLOCK AND DATA RECOVERY CIRCUIT WITHOUT AN EXTERNAL REFERENCE CLOCK
App. No. 13/619,108
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HIGH VOLTAGE HIGH PACKAGE PRESSURE SEMICONDUCTOR PACKAGE
App. No. 13/604,396
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MILLIMETER WAVE ENERGY SENSING WAND AND METHOD
App. No. 13/565,598
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Over-Sampled Single-Sided Subband Echo Cancellation
App. No. 13/562,175
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EMI SUPPRESSION WITH SHIELDED COMMON MODE CHOKE
App. No. 13/545,059
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FAST CARRY LOOKAHEAD CIRCUITS
App. No. 13/494,850
→
Photo-Voltaic Safety De-Energizing Device
App. No. 13/478,125
→
INTEGRATED CIRCUIT PACKAGE WITH DISCRETE COMPONENTS SURFACE MOUNTED ON EXPOSED SIDE
App. No. 13/473,069
→
SYSTEM AND METHOD FOR SQUELCHING A RECOVERED CLOCK IN AN ETHERNET NETWORK
App. No. 13/471,195
→
NETWORK DISTRIBUTED PACKET-BASED SYNCHRONIZATION
App. No. 13/470,197
→
TIMING SYNCHRONIZATION FOR NETWORKS WITH RADIO LINKS
App. No. 13/470,092
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FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES
App. No. 13/463,232
→
DIFFERENCE AMPLIFIER ARRANGEMENT WITH TRANSCONDUCTANCE AMPLIFIER BASED CURRENT COMPENSATION
App. No. 13/462,892
→
HIGH EFFICIENCY LED DRIVING METHOD
App. No. 13/461,793
→
APPARATUS AND METHODS FOR A TAMPER RESISTANT BUS FOR SECURE LOCK BIT TRANSFER
App. No. 13/450,765
→
TAPERED ATTENUATOR NETWORK FOR MITIGATING EFFECTS OF DIRECT CURRENT (DC) BIAS INDUCTOR SELF-RESONANCE IN TRAVELING WAVE AMPLIFIERS
App. No. 13/436,802
→
BRIGHTNESS CONTROL FOR LED LIGHTING
App. No. 13/423,395
→
METHOD AND APPARATUS FOR WIDEBAND AND SUPER-WIDEBAND TELEPHONY
App. No. 13/418,757
→
NON-VOLATILE MEMORY ARRAY ARCHITECTURE OPTIMIZED FOR HI-RELIABILITY AND COMMERCIAL MARKETS
App. No. 13/416,192
→
SYSTEM AND METHOD FOR OVERLAYING COMPUTER GENERATED HIGHLIGHTS IN A DISPLAY OF MILLIMETER WAVE IMAGERY
App. No. 13/372,253
→
USER CONTROL OF AN LED LUMINAIRE FOR A PHASE CUT DIMMER
App. No. 13/353,340
→
SILICON CARBIDE VERTICAL-SIDEWALL DUAL-MESA STATIC INDUCTION TRANSISTOR
App. No. 13/324,601
→
MOTOR NOISE REDUCTION CIRCUIT
App. No. 13/316,902
→
DIFFERENTIAL SIGNAL TERMINATION CIRCUIT
App. No. 13/314,767
→
PRECISE CLOCK SYNCHRONIZATION OVER OPTICAL FIBER
App. No. 13/309,500
→
HYSTERETIC VOLTAGE CONVERTER WITH OFFSET VOLTAGE CORRECTION
App. No. 13/305,759
→
FEEDBACK OF OUTPUT VOLTAGE ERROR VIA CURRENT SENSE WINDING
App. No. 13/304,349
→
RAM BLOCK DESIGNED FOR EFFICIENT GANGING
App. No. 13/285,210
→