TID hardened and single event transient single event latchup resistant MOS transistors and fabrication process
A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring.
1. A radiation-hardened transistor, comprising:
a p-type body well disposed in triple-well structure including a p-type substrate, a deep n-type well disposed in the p-type substrate, the p-type body well disposed in the deep n-well;
an active region within the p-type body well having a perimeter defined by a shallow trench isolation region filled with a dielectric material;
spaced-apart n-type source and drain regions disposed in the active region, forming a channel therebetween;
a polysilicon gate disposed above, aligned with, and insulated from the channel region; and
a p-type isolation region in the p-type body well formed on an inner sidewall of the shallow trench isolation region, the p-type isolation region spaced apart from the drain region separating outer edges of at least the drain region from the perimeter of the active region.
2. The transistor of claim 1 , wherein the p-type isolation region separates outer edges of the source and drain regions from the perimeter of the active region.
3. The transistor of claim 1 , further including a lightly-doped n-type region surrounding the outer edges of at least one of the source and drain regions, wherein the p-type isolation region is disposed outside of the lightly-doped n-type region.
4. The transistor of claim 1 , further including lightly-doped n-type regions at outer peripheries of each of the source and drain regions.
5. The transistor of claim 1 , wherein a portion of the p-type body well separates an inner edge of the p-type isolation region from the outer edges of at least the drain region.
6. The transistor of claim 1 , wherein a portion of the p-type body well separates an inner edge of the p-type isolation region from the outer edges of the source and drain regions.
7. A radiation-hardened transistor, comprising:
a p-type body well disposed in triple-well structure including a p-type substrate, a deep n-type well disposed in the p-type substrate, the p-type body well disposed in the deep n-well;
an active region within the p-type body well having a perimeter defined by a shallow trench isolation region filled with a dielectric material;
spaced-apart n-type source and drain regions disposed in the active region, forming a channel therebetween;
a polysilicon gate disposed above, aligned with, and insulated from the channel region; and
a first p-type isolation region in the p-type body well formed at an inner sidewall of the shallow trench isolation region at the surface of the p-type body well, the p-type isolation region spaced apart from the drain region separating outer edges of at least the drain region from the perimeter of the active region.
8. The transistor of claim 7 , wherein the first p-type isolation region includes a p-type implant at the surface of the active region.
9. The transistor of claim 8 , further including a second p-type implant disposed below the first p-type implant and formed on an inner sidewall of the shallow trench isolation region.
10. The transistor of claim 7 , further including a body contact disposed in the first p-type implant.
11. The transistor of claim 9 , wherein the second p-type implant is doped to a concentration lighter than the concentration of first p-type implant.
12. The transistor of claim 9 , further including a third p-type implant disposed below the second p-type implant and formed on an inner sidewall of the shallow trench isolation region.
13. The transistor of claim 11 , wherein the second and third p-type implants are doped to a lighter concentration than the first p-type implant.
14. The transistor of claim 10 , wherein the body contact is a salicided contact.
15. A radiation-hardened transistor, comprising:
a p-type body well disposed in triple-well structure including a p-type substrate, a deep n-type well disposed in the p-type substrate, the p-type body well disposed in the deep n-well;
an active region within the p-type body having a perimeter defined by a shallow trench isolation region filled with a dielectric material;
spaced-apart n-type source and drain regions disposed in the active region, forming a channel therebetween;
a polysilicon gate disposed above, aligned with, and insulated from the channel region; and
a p-type isolation region in the p-type body formed on an inner sidewall of the shallow trench isolation region, the p-type isolation region separating outer edges of at least the drain region from the perimeter of the active region.
16. The transistor of claim 15 , wherein the p-type isolation region separates outer edges of the source and drain regions from the perimeter of the active region.
17. The transistor of claim 15 , further including a lightly-doped n-type region surrounding the outer edges of at least one of the source and drain regions, wherein the p-type isolation region is disposed outside of the lightly-doped n-type region.
18. The transistor of claim 15 , further including lightly-doped n-type regions at outer peripheries of each of the source and drain regions.
19. The transistor of claim 15 , wherein a portion of the p-type body separates an inner edge of the p-type isolation region from the outer edges of at least the drain region.
20. The transistor of claim 15 , wherein a portion of the p-type body well separates an inner edge of the p-type isolation region from the outer edges of the source and drain regions.