TID HARDENED MOS TRANSISTORS AND FABRICATION PROCESS
A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region.
1 . A radiation-hardened transistor, comprising:
a p-type body;
an active region within the p-type body having a perimeter defined by a shallow-trench isolation region filled with a dielectric material;
spaced-apart source and drain regions disposed in the active region, forming a channel therebetween;
a polysilicon gate disposed above, aligned with, and insulated from the channel region; and
a p-type isolation ring in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region.
2 . The transistor of claim 1 wherein the p-type body is a p-type body well disposed in triple-well HV well structure including a p-type substrate, a deep n-type well disposed in the p-type substrate, the p-type body well disposed in the deep n-well.
3 . The transistor of claim 1 wherein the p-type isolation ring separates outer edges of both the source and drain regions from the perimeter of the active region.
4 . The transistor of claim 1 , wherein the p-type isolation ring includes a first portion adjacent to the outer edges of at least one of the source and drain regions from the perimeter of the active region and a second portion outside of the first portion extending to the perimeter of the active region.
5 . The transistor of claim 1 further including by a lightly-doped n-type region surrounding the outer edges of at least one of the source and drain regions and wherein the p-type isolation ring is disposed outside of the lightly-doped n-type region.
6 . The transistor of claim 4 , wherein the first portion of the p-type isolation ring comprises a portion of the p-type substrate.
7 . The transistor of claim 1 , further including lightly-doped regions at outer peripheries of the source and drain regions.
8 . The transistor of claim 7 , wherein the second portion of the p-type isolation region includes a first p-type implant at the surface of the active region.
9 . The transistor of claim 8 , wherein the second portion of the p-type isolation region further includes a second p-type implant disposed below the first p-type implant.
10 . The transistor of claim 9 , wherein the second p-type implant is lighter than the first p-type implant.
11 . The transistor of claim 9 , wherein the second portion of the p-type isolation region further includes a third p-type implant disposed below the second p-type implant.
12 . The transistor of claim 11 , wherein the second p-type implant is lighter than the first p-type implant, and the third p-type implant is lighter than the second p-type implant.