IP Library › Assignment 046251/0391
Patent Assignment
Reel/Frame 046251/0391

RELEASE OF SECURITY INTEREST

Recorded: 2018-05-29 Received: 2018-05-29 Pages: 98
Assignor
Assignees
MICROSEMI CORPORATION
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
MICROSEMI SEMICONDUCTOR (U.S.), INC.
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
MICROSEMI FREQUENCY AND TIME CORPORATION
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
MICROSEMI COMMUNICATIONS, INC.
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
MICROSEMI SOC CORP.
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
MICROSEMI CORP. - POWER PRODUCTS GROUP
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
ONE ENTERPRISE, ALISO VIEJO, CA, 92656, UNITED STATES
Covered Applications (100)
MULTI-STATE CONFIGURATION RAM CELL
App. No. 14/950,114
→
SECURITY METHOD AND APPARATUS TO PREVENT REPLAY OF EXTERNAL MEMORY DATA TO INTEGRATED CIRCUITS HAVING ONLY ONE-TIME PROGRAMMABLE NON-VOLATILE MEMORY
App. No. 14/941,991
→
SOLID-STATE PHOTODETECTOR WITH A SPECTRAL RESPONSE OF THE GENERATED PHOTOCURRENT IS CONTROLLED BY AN APPLIED BIAS VOLTAGE (As amended)
App. No. 14/936,716
→
RESISTIVE RANDOM ACCESS MEMORY CELLS
App. No. 14/835,928
→
DISPLAY SCREEN WITH ICON
App. No. 29/533,488
→
METHOD FOR IMPLEMENTING "INSTANT BOOT" IN A CUSTOMIZABLE SOC
App. No. 14/790,248
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APPARATUS AND METHOD FOR DETECTING AND PREVENTING LASER INTERROGATION OF AN FPGA INTEGRATED CIRCUIT
App. No. 14/790,982
→
IDENTIFYING INTEGRATED CIRCUIT ORIGIN USING TOOLING SIGNATURE
App. No. 14/747,758
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TIMESTAMP PREDICTOR FOR PACKETS OVER A SYNCHRONOUS PROTOCOL
App. No. 14/721,920
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APPARATUS AND METHOD FOR DETECTION OF OFF-HOOK PHONE IN REVERSE POWER FEEDING ARCHITECTURE
App. No. 14/710,611
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Circuit and Method for Reducing BVii on Highly Overdriven Devices
App. No. 14/703,710
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Gate Boosting Transmission Gate
App. No. 14/703,720
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Inductive Displacement Sensor
App. No. 14/697,836
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LOAD BALANCING REVERSE POWER SUPPLY
App. No. 14/691,132
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CURRENT SENSING SYSTEM AND METHOD
App. No. 14/666,326
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METHODS FOR CONTROLLING THE USE OF INTELLECTUAL PROPERTY IN INDIVIDUAL INTEGRATED CIRCUIT DEVICES
App. No. 14/632,860
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METHODS FOR CONTROLLING THE USE OF INTELLECTUAL PROPERTY IN INDIVIDUAL INTEGRATED CIRCUIT DEVICES
App. No. 14/630,901
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SIC TRANSIENT VOLTAGE SUPPRESSOR
App. No. 14/622,309
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LAYOUTS FOR RESISTIVE RAM CELLS
App. No. 14/621,139
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HIGH EFFICIENCY LED DRIVING METHOD
App. No. 14/608,242
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METHOD AND SYSTEM FOR SYNCHRONIZING BASE STATION AND ESTABLISHING LOCATION
App. No. 14/582,147
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MULTIPLE OUTPUT SYNCHRONOUS POWER CONVERTER
App. No. 14/559,135
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SYSTEMS AND METHODS FOR A FULLY ISOLATED ENCRYPTION KEY FILLING PORT
App. No. 14/557,729
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HIGH VOLTAGE DEVICE FABRICATED USING LOW-VOLTAGE PROCESSES
App. No. 14/547,336
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CHIP-SCALE ATOMIC GYROSCOPE
App. No. 14/542,844
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ETHERNET POINT TO POINT LINK INCORPORATING FORWARD ERROR CORRECTION
App. No. 14/527,795
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CONTINUOUSLY INTERLEAVED ERROR CORRECTION
App. No. 14/526,148
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Secure Storage Devices, Authentication Devices, and Methods Thereof
App. No. 14/508,655
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VOLTAGE REGULATOR WITH CHARGE PUMP FOR GENERATING SECOND VOLTAGE SOURCE
App. No. 14/505,688
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NETWORK DISTRIBUTED PACKET-BASED SYNCHRONIZATION
App. No. 14/503,082
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PTP TRANSPARENT CLOCK SYSTEM UPGRADE SOLUTION
App. No. 14/502,877
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PACKET PROTOCOL PROCESSING WITH PRECISION TIMING PROTOCOL SUPPORT
App. No. 14/494,438
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LED LUMINAIRE DRIVING CIRCUIT AND METHOD
App. No. 14/493,411
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METHOD OF IMPROVING FPGA SECURITY USING AUTHORIZATION CODES
App. No. 14/485,833
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SONOS FPGA Architecture Having Fast Data Erase and Disable Feature
App. No. 14/481,943
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MULTI-CHANNEL LOW POWER WAKE-UP SYSTEM
App. No. 14/482,595
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RADIO WAKE-UP SYSTEM WITH MULTI-MODE OPERATION
App. No. 14/482,527
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VOLTAGE REGULATOR WITH SWITCHING AND LOW DROPOUT MODES
App. No. 14/454,134
→
HIGH EFFICIENCY PFC POWER CONVERTER
App. No. 14/446,115
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PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE
App. No. 14/337,865
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METHOD FOR EFFICIENT FPGA PACKING
App. No. 14/327,842
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METHOD FOR SECURELY BOOTING TARGET PROCESSOR IN TARGET SYSTEM USING A SECURE ROOT OF TRUST TO VERIFY A RETURNED MESSAGE AUTHENTICATION CODE RECREATED BY THE TARGET PROCESSOR
App. No. 14/322,953
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SYNCHRONOUS REGULATION FOR LED STRING DRIVER
App. No. 14/296,544
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Back to Back Resistive Random Access Memory Cells
App. No. 14/274,417
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VOIDLESSLY ENCAPSULATED SEMICONDUCTOR DIE PACKAGE
App. No. 14/258,775
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CHIP-SCALE ATOMIC GYROSCOPE
App. No. 14/250,059
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DISTRIBUTED TWO-STEP CLOCK
App. No. 14/210,913
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System on a Chip FPGA Spatial Debugging Using Single Snapshot
App. No. 14/212,508
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Background Auto-refresh Apparatus and Method for Non-Volatile Memory Array
App. No. 14/208,513
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TID HARDENED AND SINGLE EVENT TRANSIENT SINGLE EVENT LATCHUP RESISTANT MOS TRANSISTORS AND FABRICATION PROCESS
App. No. 14/196,667
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NON-VOLATILE PUSH-PULL NON-VOLATILE MEMORY CELL HAVING REDUCED OPERATION DISTURB AND PROCESS FOR MANUFACTURING SAME
App. No. 14/193,772
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DISTRIBUTION OF LOCATION INFORMATION
App. No. 14/188,398
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HYSTERETIC CURRENT MODE CONTROL CONVERTER WITH LOW, MEDIUM AND HIGH CURRENT THRESHOLDS
App. No. 14/171,843
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PACKET-BASED TIMING MEASUREMENT
App. No. 14/171,698
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TIMING SYNCHRONIZATION FOR NETWORKS WITH RADIO LINKS
App. No. 14/160,449
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NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY
App. No. 14/155,752
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RF POWER MULTI-CHIP MODULE PACKAGE
App. No. 14/153,948
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UNIVERSAL ASYMMETRY COMPENSATION FOR PACKET TIMING PROTOCOLS
App. No. 14/149,370
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PARALLEL CRC COMPUTATION WITH DATA ENABLES
App. No. 14/135,437
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INTEGRATED START-UP BIAS BOOST FOR DYNAMIC ERROR VECTOR MAGNITUDE ENHANCEMENT
App. No. 14/090,401
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LOW LOSS SIC MOSFET
App. No. 14/079,541
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HIGH ACCURACY 1588 TIMESTAMPING OVER HIGH SPEED MULTI LANE DISTRIBUTION PHYSICAL CODE SUBLAYERS
App. No. 14/041,626
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DELAY MEASUREMENT IN A POINT TO MULTIPOINT SYSTEM
App. No. 14/040,320
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AUTO-REFRESH METHOD FOR SONOS NON-VOLATILE MEMORY ARRAY
App. No. 14/013,339
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SECURE DIGEST FOR PLD CONFIGURATION DATA
App. No. 13/964,692
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APPARATUS AND METHOD FOR SENSING INCIDENT LIGHT HAVING DUAL PHOTODIODE TO ABSORB LIGHT IN RESPECTIVE DEPLETION REGIONS CONTROLLED BY DIFFERENT BIAS VOLTAGES (AS AMENDED)
App. No. 13/943,305
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ON-CHIP PROBE CIRCUIT FOR DETECTING FAULTS IN AN FPGA
App. No. 13/933,332
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ON-CHIP PROBE CIRCUIT FOR DETECTING FAULTS IN AN FPGA
App. No. 13/933,353
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FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES
App. No. 13/898,827
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INTEGRATED START-UP BIAS BOOST FOR DYNAMIC ERROR VECTOR MAGNITUDE ENHANCEMENT
App. No. 13/897,192
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INTEGRATED START-UP BIAS BOOST FOR DYNAMIC ERROR VECTOR MAGNITUDE ENHANCEMENT
App. No. 13/895,236
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INTEGRATED TECHNIQUE FOR ENHANCED POWER AMPLIFIER FORWARD POWER DETECTION
App. No. 13/894,221
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POWER OVER ETHERNET FOR BI-DIRECTIONAL ETHERNET OVER SINGLE PAIR
App. No. 13/889,391
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SQUARE LAW EXTENSION TECHNIQUE FOR HIGH SPEED RADIO DETECTION
App. No. 13/860,875
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FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS
App. No. 13/840,815
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Asymmetry Correction for Precise Clock Synchronization Over Optical Fiber
App. No. 13/800,446
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PSEUDO SELF ALIGNED RADHARD MOSFET AND PROCESS OF MANUFACTURE
App. No. 13/742,253
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PULSE TRANSFORMER DRIVER
App. No. 13/718,131
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HIGH EFFICIENCY LED DRIVING METHOD FOR ODD NUMBER OF LED STRINGS
App. No. 13/717,755
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PACKET-BASED TIMING MEASUREMENT
App. No. 13/679,672
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PHYSICAL LAYER PROCESSING OF TIMESTAMPS AND MAC SECURITY
App. No. 13/671,480
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WAN TRANSPORT OF FRAMES WITH MAC SECURITY
App. No. 13/671,516
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APPARATUS AND METHOD FOR ASSESSING VOLUMETRIC MOISTURE CONTENT AND CONTROLLING AN IRRIGATOR
App. No. 13/665,871
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CONVERTER WITH HYSTERETIC CONTROL
App. No. 13/659,046
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METHOD AND APPARATUS FOR LED STRING SHORT CIRCUIT DETECTION AND PROTECTION
App. No. 13/652,495
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CONTINUOUSLY INTERLEAVED ERROR CORRECTION
App. No. 13/618,380
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FREQUENCY AND PHASE ACQUISITION OF A CLOCK AND DATA RECOVERY CIRCUIT WITHOUT AN EXTERNAL REFERENCE CLOCK
App. No. 13/619,108
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EMI SUPPRESSION WITH SHIELDED COMMON MODE CHOKE
App. No. 13/545,059
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Millimeter Wave Imaging Method and System to Detect Concealed Objects
App. No. 13/540,340
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FAST CARRY LOOKAHEAD CIRCUITS
App. No. 13/494,850
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Photo-Voltaic Safety De-Energizing Device
App. No. 13/478,125
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SYSTEM AND METHOD FOR SQUELCHING A RECOVERED CLOCK IN AN ETHERNET NETWORK
App. No. 13/471,195
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NETWORK DISTRIBUTED PACKET-BASED SYNCHRONIZATION
App. No. 13/470,197
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TIMING SYNCHRONIZATION FOR NETWORKS WITH RADIO LINKS
App. No. 13/470,092
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FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES
App. No. 13/463,232
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DIFFERENCE AMPLIFIER ARRANGEMENT WITH TRANSCONDUCTANCE AMPLIFIER BASED CURRENT COMPENSATION
App. No. 13/462,892
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HIGH EFFICIENCY LED DRIVING METHOD
App. No. 13/461,793
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APPARATUS AND METHODS FOR A TAMPER RESISTANT BUS FOR SECURE LOCK BIT TRANSFER
App. No. 13/450,765
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TAPERED ATTENUATOR NETWORK FOR MITIGATING EFFECTS OF DIRECT CURRENT (DC) BIAS INDUCTOR SELF-RESONANCE IN TRAVELING WAVE AMPLIFIERS
App. No. 13/436,802
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BRIGHTNESS CONTROL FOR LED LIGHTING
App. No. 13/423,395
→