Low loss SiC MOSFET
View Patent ↗A Vertical Multiple Implanted Silicon Carbide Power MOSFET (VMIMOSFET) includes a first conductivity semiconductor substrate, a first conductivity semiconductor drift layer on the top of the substrate, a multitude of second conductivity layers implanted in the drift layer. The body layer is where the channel is formed. A first conductivity source layer is interspaced appropriately inside of the second conductivity layers. A gate oxide of a certain thickness and another oxide of a different thickness, a greater thickness than the gate oxide, placed in between the body layers but in such way that its shape does not distort the gate oxide in the channel. A charge compensated body layer of the second conductivity formed outside of the channel region and only at specific high electric field locations in the structure. The device and the manufacturing method deliver a power SiC MOSFET with increased frequency of operation and reduced switching losses.
1. A process for fabrication of a silicon carbide (SiC) vertical power MOSFET structure, the process comprising:
providing a SiC substrate including an upper layer of a first dopant type defining a drift region extending from an upper surface of the substrate depthwise into the substrate;
implanting a pair of body regions in the upper layer and adjoining the upper surface of the substrate, the body regions being spaced apart about the drift region and of a second dopant type opposite the first dopant type, each of the body regions having opposite lateral peripheries each forming a first PN junction with the drift region;
implanting a pair of source regions spaced apart in each body region across the upper surface of the substrate to define a source contact region and positioned with respect to the lateral peripheries of the body region to form a second PN junction spaced laterally from the first PN junction and to define a channel region along the upper surface between the first and second PN junctions;
forming a gate oxide layer of a first thickness on the upper surface extending over each channel region;
forming a gate conductor contacting the gate oxide layer;
forming a source conductor contacting the source regions and the body region therebetween; and
forming a terraced dielectric layer on the upper surface extending between each of the gate oxide layers over the drift region, the terraced dielectric layer having a second thickness greater than the first thickness of the gate oxide layer;
wherein the terraced dielectric layer includes opposite tapered edges which intercept the body regions at the upper surface of the substrate adjacent the first PN junctions and which overlap portions of the body regions within the substrate below the upper surface.
2. The SiC power MOSFET process of claim 1 , including implanting a pair of regions of the first dopant type to form counterdoped regions along the opposite lateral peripheries of the body regions, the counterdoped regions spaced below each channel region and away from the source regions and having a doping concentration less than a doping concentration of the body region at the upper surface.
3. The SiC power MOSFET process of claim 1 , including implanting a JFET region of the first dopant type in an upper portion of the upper layer, to enhance a doping concentration of the drift region around the body region.
4. The SiC power MOSFET process of claim 3 , in which the JFET region encompasses the pair of body regions.
5. The SiC power MOSFET process of claim 1 , including implanting an unclamped inductive switching (UIS) region of the second dopant type in the upper layer spaced laterally inward from each channel region beneath the source regions, to enhance a doping concentration of the body region beneath the source regions.
6. The SiC power MOSFET process of claim 1 , in which providing the SiC substrate includes forming a bottom layer of the second dopant type opposite the first dopant type such that the structure is operative as an insulated gate bipolar transistor (IGBT).
7. The SiC power MOSFET process of claim 1 , wherein the terraced dielectric layer is formed on the upper surface of the substrate after implanting the pair of body regions and the pair of source regions.
8. A process for fabrication of a silicon carbide (SiC) vertical power MOSFET structure, the process comprising:
providing a SiC substrate including an upper layer of a first dopant type defining a drift region extending from an upper surface of the substrate depthwise into the substrate;
implanting a body region in the upper layer and adjoining the upper surface of the substrate, the body region being of a second dopant type opposite the first dopant type and having opposite lateral peripheries each forming a first PN junction with the drift region;
implanting a pair of source regions spaced apart in the body region across the upper surface of the substrate to define a source contact region and positioned with respect to the lateral peripheries of the body region to form a second PN junction spaced laterally from the first PN junction and to define a channel region along the upper surface between the first and second PN junctions;
forming a gate oxide layer on the upper surface extending over each channel region;
forming a gate conductor contacting the gate oxide;
forming a source conductor contacting the source regions and the body region therebetween; and
implanting a pair of regions of the first dopant type to faun counterdoped regions along the opposite lateral peripheries of the body regions, the counterdoped regions spaced below each channel region and away from the source regions and having a doping concentration less than a doping concentration of the body region at the upper surface.
9. The SiC power MOSFET process of claim 8 , in which the gate oxide layer has a first thickness, the process further including forming a terraced dielectric layer on the upper surface extending laterally from the gate oxide layer over the drift region, the terraced dielectric layer having a second thickness greater than the first thickness of the gate oxide layer.
10. The SiC power MOSFET process of claim 8 , including implanting a JFET region of the first dopant type in an upper portion of the upper layer, to enhance a doping concentration of the drift region around the body region.
11. The SiC power MOSFET structure of claim 8 , including implanting an unclamped inductive switching (UIS) region of the second dopant type in the upper layer spaced laterally inward from the channel regions beneath the source regions, to enhance a doping concentration of the body region beneath the source regions.