IP Library Granted Patent US 9,264,132
Granted Patent B2
US 9,264,132 · App. 14/149,370 · Granted Feb 16, 2016

Universal asymmetry compensation for packet timing protocols

Inventor: George P. Zampetti (Livermore, CA)
Assignee: Microsemi Frequency and Time Corporation
H04B10/07H04J3/0644H04J3/0658H04J3/0667
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Quick Facts
Patent No.
US 9,264,132
App. No.
14/149,370
Granted
Feb 16, 2016
Kind
B2
Abstract

The notion of a “PTP aware” path is one current proposed approach to reduce asymmetry effects. In a fully PTP aware path there is the notion of on-path support mechanisms such as boundary clocks and transparent clocks at every switching or routing node. However, on-path support methods only address time-transfer errors introduced inside network elements and any asymmetry in the transmission medium, such as, for example, the fiber strands for the two directions of transmission, cannot be compensated for by on-path support mechanisms. Furthermore, in a real operational network, which may traverse different operational domains administered by different entities, full on-path support is a difficult challenge. In certain managed network scenarios full on-path support can be contemplated. Nevertheless, the universal asymmetry compensation method described herein mitigates the asymmetry in a network path, without requiring on-path support mechanisms such as transparent clocks and boundary clocks.

Claims (34)

1. A method of correcting a clock, comprising:

determining if a table, which stores asymmetry time error estimates for one or more network paths, includes an entry associated with a given network path, wherein each of the asymmetry time error estimates stored in the table is obtained with global navigation satellite systems (GNSS) support;

if the table includes the entry associated with the given network path, correcting, based on an asymmetry time error estimate for the entry, a time delay estimated using timing packets received over the given network path; and

correcting the clock based on the corrected time delay estimate and time contained in the timing packets.

2. The method of claim 1 , wherein the entry associated with the given network path is identified based on a corresponding signature determined from the received timing packets.

3. The method of claim 2 , wherein the signature comprises a roundtrip delay estimate.

4. The method of claim 3 , wherein identifying the entry associated with the given network path comprises:

determining if the table includes a candidate entry for a roundtrip delay window which matches the roundtrip delay estimated from the received timing packets; and

if the table includes the candidate entry, validating the candidate entry using hypothesis testing.

5. The method of claim 2 , wherein the signature comprises transit delay estimates determined using the given network path with and without on-path support.

6. The method of claim 1 , wherein each of the asymmetry time error estimates stored in the table is obtained by determining a difference between time error estimated using GNSS timing signals and time error estimated using timing packets transmitted over a respective network path.

7. The method of claim 6 , wherein, for each asymmetry time error estimate, the time error difference is estimated in N non-overlapping time windows, and a clustering algorithm is applied using the time error differences in the N non-overlapping time windows to obtain the asymmetry time error estimate.

8. The method of claim 1 , wherein the GNSS support is provided in one of a direct support operating mode in which asymmetry mitigation is directly traceable to Coordinated Universal Time (UTC) via time traceability of a GNSS system, and an indirect support operating mode in which asymmetry mitigation is traceable to an originating grandmaster device timescale.

9. The method of claim 1 , further comprising combining time alignment determined using GNSS timing signals and time alignment determined using the timing packets to achieve robustness.

10. The method of claim 1 , wherein the table storing asymmetry time error estimates is maintained for a single master or grandmaster device from which timing packets are received.

11. A clock device, comprising:

a memory configured to store a table which includes asymmetry time error estimates for one or more network paths, wherein each of the asymmetry time error estimates is obtained with global navigation satellite systems (GNSS) support; and

a processing unit programmed to correct a clock by performing steps comprising:

determining if the table includes an entry associated with a given network path,

if the table includes the entry associated with the given network path, correcting, based on an asymmetry time error estimate for the entry, a time delay estimated using timing packets received over the given network path, and

correcting the clock based on the corrected time delay estimate and time contained in the timing packets.

12. The device of claim 11 , wherein the entry associated with the given network path is identified based on a corresponding signature determined from the received timing packets.

13. The device of claim 12 , wherein the signature comprises a roundtrip delay estimate.

14. The device of claim 13 , wherein identifying the entry associated with the given network path comprises:

determining if the table includes a candidate entry for a roundtrip delay window which matches the roundtrip delay estimated from the received timing packets; and

if the table includes the candidate entry, validating the candidate entry using hypothesis testing.

15. The device of claim 12 , wherein the signature comprises transit delay estimates determined using the given network path with and without on-path support.

16. The device of claim 11 , wherein each of the asymmetry time error estimates stored in the table is obtained by determining a difference between time error estimated using GNSS timing signals and time error estimated using timing packets transmitted over a respective network path.

17. The device of claim 16 , wherein, for each asymmetry time error estimate, the time error difference is estimated in N non-overlapping time windows, and a clustering algorithm is applied using the time error differences in the N non-overlapping time windows to obtain the asymmetry time error estimate.

18. The device of claim 11 , wherein the GNSS support is provided in one of a direct support operating mode in which asymmetry mitigation is directly traceable to Coordinated Universal Time (UTC) via time traceability of a GNSS system, and an indirect support operating mode in which asymmetry mitigation is traceable to an originating grandmaster device timescale.

19. The device of claim 11 , the steps further comprising, combining time alignment determined using GNSS timing signals and time alignment determined using the timing packets to achieve robustness.

20. A method of correcting asymmetry for packet timing protocols in response to a path disruption, the method comprising:

calibrating asymmetry by determining, for a first network path, an asymmetry correction from one of (1) a difference between time error estimated using global navigation satellite systems (GNSS) timing signals and time error estimated using timing packets transmitted over the network path, and (2) a table storing previously determined asymmetry corrections for one or more network paths; and

correcting a clock based on a time delay which is estimated from time contained in the timing packets transmitted over the network path and corrected based on the asymmetry correction.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
SECURITY AGREEMENT Recorded Apr 22, 2015
From: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP; MICROSEMI SEMICONDUCTOR (U.S.) INC.; MICROSEMI SOC CORP.; MICROSEMI FREQUENCY AND TIME CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 035477/0057 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2014
From: ZAMPETTI, GEORGE P.
To: MICROSEMI FREQUENCY AND TIME CORPORATION
Reel/Frame 032468/0417 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2014
From: ZAMPETTI, GEORGE P.
To: MICROSEMI CORPORATION
Reel/Frame 031907/0816 →
Continuity (2)
Provisional Application 61749565 · Jan 7, 2013
Related Publication 20140192826A1 · Jul 10, 2014