Apparatus and method for detecting and preventing laser interrogation of an FPGA integrated circuit
View Patent ↗A circuit internal to a programmable integrated circuit for preventing laser interrogation of the programmable integrated circuit includes a sense resistor connected between a deep n-well and a source of bias voltage for the deep n-well. A voltage-sensing circuit is coupled across the sense resistor to measure voltage across the sense resistor. A tamper trigger circuit responsive to the voltage sensing circuit generates a tamper signal in response to a voltage sensed in the voltage sensing circuit having a magnitude greater than a threshold value.
1. A circuit internal to a programmable integrated circuit for preventing laser interrogation of the programmable integrated circuit and comprising:
a deep n-well containing transistors in the programmable integrated circuit formed on a p-type substrate;
a source of bias voltage for the deep n-well, the bias voltage arranged to provide a reverse bias for the n-well in respect to the p-type substrate;
a sense resistor connected between the deep n-well and the source of bias voltage;
a voltage-sensing circuit coupled across the sense resistor to measure voltage across the sense resistor; and
a tamper trigger circuit responsive to the voltage sensing circuit to generate a tamper signal in response to a voltage sensed in the voltage sensing circuit having a magnitude greater than a threshold value.
2. The circuit of claim 1 , further comprising a disable circuit responsive to the tamper signal by disabling at least one function of the programmable integrated circuit.
3. The circuit of claim 1 , further comprising:
program and erase circuitry on the integrated circuit configured to program and erase configuration elements on the programmable integrated circuit, the program and erase circuitry on the integrated circuit configured to erase the configuration elements in response to the tamper signal.
4. A method for preventing laser interrogation of the programmable integrated circuit and comprising:
measuring current flowing between a deep-n-well in the integrated circuit and a voltage bias source for the deep n-well in the integrated circuit;
generating a tamper signal when the current flowing between the deep-n-well and the voltage bias source for the deep n-well exceeds a threshold value; and
causing an anti-tampering action in the integrated circuit in response to the tamper signal.
5. The method of claim 4 , wherein causing an anti-tampering action in the integrated circuit in response to the tamper signal comprises disabling at least one clock circuit in the programmable integrated circuit.
6. The method of claim 4 , wherein causing an anti-tampering action in the integrated circuit in response to the tamper signal comprises disabling at least one function of the programmable integrated circuit.
7. The method of claim 4 , wherein causing an anti-tampering action in the integrated circuit in response to the tamper signal comprises erasing a configuration memory in the integrated circuit.