System on a chip FPGA spatial debugging using single snapshot

1. A method for performing on-chip spatial debugging of a user circuit programmed into a user-programmable integrated circuit to be provided to a user, the method comprising:

operating the integrated circuit in a system for which the user circuit was designed;

halting during an Nth clock cycle an internal clock driving synchronous logic elements in the integrated circuit in response to an output state transition of a sequential logic element in the integrated circuit triggered by a clock transition occurring during the Nth clock cycle, the sequential logic element being arbitrarily selected from among all of the synchronous logic elements in the integrated circuit during performance of the on-chip spatial debugging of the user circuit;

reading the states of at least some of synchronous logic elements programmed into the integrated circuit while the internal clock is halted;

while the internal clock is halted, forcing an output of at least one synchronous logic element to an arbitrary desired state selected during performance of the on-chip spatial debugging of the user circuit; and

restarting the internal clock.

2. The method of claim 1 further comprising generating an interrupt to an embedded processor in the integrated circuit running a user application in response to the output state of the sequential logic element in the integrated circuit.

3. The method of claim 1 wherein restarting the internal clock comprises restarting the internal clock for a single clock pulse following forcing the output of at least one synchronous logic element to a desired state, the method further comprising:

halting the internal clock following the single clock pulse;

reading the states of all synchronous logic elements programmed into the integrated circuit after the internal clock is halted following the single clock pulse.

4. The method of claim 1 further comprising halting a clock driving an embedded processor in the integrated circuit running a user application simultaneously with halting the internal clock driving synchronous logic elements.

5. The method of claim 1 wherein reading the states of at least some of synchronous logic elements programmed into the integrated circuit while the internal clock is halted comprises reading the states of all of the synchronous logic elements programmed into the integrated circuit while the internal clock is halted.